参数资料
型号: MAX1967EUB+T
厂商: Maxim Integrated Products
文件页数: 11/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 127kHz
占空比: 95%
电源电压: 2.7 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
Low-Cost Voltage Mode PWM
Step-Down Controller
4) Select compensation capacitor C 6 so that the error
amp zero is equal to the complex pole frequency
LC of the inductor and output capacitor:
5V TO 28V FOR
GATE BIAS
VIN
VL
3.3V
VCC
INPUT
C 6 =
L × C OUT
R 3
BST
DH
V OUT
Input Capacitor Selection
The input capacitor (C 2 ) reduces noise injection and
the current peaks drawn from the input supply. The
MAX1967
LX
source impedance to the input supply determines the
value of C 2 . High source impedance requires high
input capacitance. The input capacitor must meet the
COMP/EN
DL
ripple current requirement (I RMS ) imposed by the
switching currents. The RMS input ripple current is
given by:
GND
FB
R2
R1
I RMS = I LOAD ×
V OUT × ( V VIN ? V OUT )
V VIN
Figure 5. Low Input Voltage Step-Down with Extra Bias Supply
P D ( N 2 ) = ? 1 ? OUT ? × I LOAD 2 × R DS ( ON )
For  optimal  circuit  reliability,  choose  a  capacitor  that
has less than a 10 ° C temperature rise at the peak rip-
ple current.
Power MOSFET Selection
The MAX1966/MAX1967s ’ step-down controller drives
two external logic-level N-channel MOSFETs. The key
selection parameters are:
1) On-resistance (R DS(ON) ) of both MOSFETs for cur-
rent limit and efficiency
2) Current capability of V L (MAX1967 only) and gate
charge (Q T )
3) Voltage rating and maximum input voltage
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
input voltage:
for Gate Drive
where C RSS is the reverse transfer capacitance of N1
and I GATE is the peak gate-drive source/sink current
(1A typical). For the low-side N-FET (N2), the worst-
case power dissipation occurs at maximum input volt-
age:
? V ?
? V VIN ?
The low-side MOSFET on-resistance sets the
MAX1966/MAX1967 current limit. See the Setting the
Current Limit section for information on selecting low-
side MOSFET R DSON . For designs supplying 5A or
less, it is often possible to combine the high-side and
low-side MOSFETs into a single package (usually an 8-
pin SO) as indicated in Table 1. For higher output appli-
cations, or those where efficiency is more important,
P D ( N 1 RESISTIVE ) =
V OUT
V VIN ( MIN )
× I LOAD 2 × R DS ( ON )
separate FETs are usually preferred.
Very-Low-Voltage Applications
The MAX1966/MAX1967 are extremely versatile con-
trollers that can be used in a variety of applications
P D ( N 1 / SWITCHING ) = × V VIN ( MAX ) 2 × f OSC RSS
× C
The  following  switching  loss  calculation  for  the  high-
side N-FET provides an approximation, but is no substi-
tute for evaluation:
I LOAD
I GATE
where high efficiency, high output power, and opti-
mized cost are important. One alternate connection,
shown in Figure 5, is useful when a low-voltage supply
is to be stepped down to an even lower voltage at high
current. If an additional bias supply is available, it can
supply gate drive separately from the input power rail.
This can either improve efficiency, or allow lower cost
5V logic-level MOSFETs to be used in place of 3V
MOSFETs.
______________________________________________________________________________________
11
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