- 您现在的位置：买卖IC网 > PDF目录383343 > MAX19700 (Maxim Integrated Products, Inc.) 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End PDF资料下载
参数资料
| 型号： | MAX19700 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End |
| 中文描述： | 7.5Msps、超低功耗模拟前端 |
| 文件页数： | 7/37页 |
| 文件大小： | 561K |
| 代理商： | MAX19700 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
M
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33μF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Q-DAC DATA to CLK Rise Setup
Time
t
DSQ
Figure 5 (Note 6)
9
ns
CLK Fall to I-DAC Data Hold Time
t
DHI
Figure 5 (Note 6)
-4
ns
CLK Rise to Q-DAC Data Hold
Time
t
DHQ
Figure 5 (Note 6)
-4
ns
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6)
50
±15
2.6
%
%
ns
20% to 80%
Falling Edge of
CS
to Rising Edge
of First SCLK Time
t
CSS
10
ns
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to
CS
Setup Time
CS
High Pulse Width
CS
High to DOUT Active High
t
DS
t
DH
t
CH
t
CL
t
CP
t
CS
t
CSW
t
CSD
10
0
25
25
50
10
80
ns
ns
ns
ns
ns
ns
ns
ns
Bit AD0 set
200
CS
High to DOUT Low (Aux-ADC
Conversion Time)
t
CONV
Bit AD0 set, no averaging (see Table 14),
f
CLK
= 45MHz,
CLK divider = 16 (see Table 15)
4.27
μs
DOUT Low to
CS
Setup Time
SCLK Low to DOUT Data Out
CS
High to DOUT High Impedance
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
t
DCS
t
CD
t
CHZ
Bit AD0, AD10 set
Bit AD0, AD10 set
Bit AD0, AD10 set
200
ns
ns
ns
14.5
200
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
85.2
Shutdown Wake-Up Time
t
WAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
28.2
μs
Fr om i d e to Rx m od e w h C LK p esent
d ur ng i d e, AD C settl es to w hi n 1d B S N AD
9.8
Idle Wake-Up Time (With CLK)
t
WAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
6.4
μs
From standby to Rx mode, ADC settles to
within 1dB SINAD
13.7
Standby Wake-Up Time
t
WAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error
24
μs
相关PDF资料 |
PDF描述 |
|---|---|
| MAX19705 | 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End |
| MAX19706 | 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End |
| MAX19707 | 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End |
| MAX19707ETM | 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End |
| MAX19708 | 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX19700ETM | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| MAX19700ETM+ | 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| MAX19700ETM+T | 功能描述:ADC / DAC多通道 7.5Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| MAX19700ETM-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| MAX19700EVCMOD2 | 功能描述:ADC / DAC多通道 Evaluation Kit/Evaluation System for the MAX19700 RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
发布紧急采购，3分钟左右您将得到回复。