参数资料
型号: MAX1992ETG+T
厂商: Maxim Integrated Products
文件页数: 13/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-TQFN
标准包装: 2,500
系列: Quick-PWM™
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
Quick-PWM Step-Down Controllers with Inductor
Saturation Protection and Dynamic Output Voltages
Pin Description (continued)
MAX1992
PIN
MAX1993
NAME
FUNCTION
Negative Current-Sense Input. Connect to the negative terminal of the current-sense
12
12
CSN
element. Figure 10 and Table 7 describe several current-sensing options. The PWM
controller does not begin a cycle unless the current sensed is less than the valley
current-limit threshold programmed at ILIM.
Pulse-Skipping Control Input. Connect SKIP to V CC for low-noise, forced-PWM mode
13
13
SKIP
or connect SKIP to analog ground (AGND or GND) to enable pulse-skipping
operation.
Battery Voltage-Sense Connection. The controller only uses V+ to set the on-time one-
14
14
V+
shot timing. The DH on-time is inversely proportional to input voltage over a range of
2V to 28V.
15
16
15
16
DH
LX
High-Side Gate-Driver Output. DH swings from LX to BST.
Inductor Connection. Connect LX to the switched side of the inductor. LX serves as
the lower supply rail for the DH high-side gate driver.
Boost Flying Capacitor Connection. Connect to an external capacitor and diode as
17
17
BST
shown in Figure 6. An optional resistor in series with BST allows the DH pullup current
to be adjusted.
18
19
20
21
18
19
20
DL
V DD
PGND
GND
AGND
Low-Side Gate-Driver Output. DL swings from PGND to V DD (MAX1992) or GND to
V DD (MAX1993).
Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage
(+4.5V to +5.5V). Bypass V DD to PGND with a 1μF or greater ceramic capacitor.
Power Ground. Ground connection for the DL low-side gate driver.
Analog and Power Ground. AGND and PGND connect together internally. Connect
backside pad to GND.
Analog Ground. Connect backside pad to AGND.
Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal
21
GATE
MOSFET so OD appears as a high impedance. A logic high on GATE turns on the
internal MOSFET, pulling OD to ground.
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through
22
22
V CC
a series 20 Ω resistor. Bypass V CC to analog ground with a 1μF or greater ceramic
capacitor.
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13
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