参数资料
型号: MAX2021ETX+T
厂商: Maxim Integrated
文件页数: 16/20页
文件大小: 0K
描述: IC MOD/DEMOD 36-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 调制器/解调器
频率: 750MHz ~ 1.2GHz
RF 型: GSM,EDGE,CDMA
次要属性: 升/降频器
封装/外壳: 36-WFQFN 裸露焊盘
包装: 带卷 (TR)
MAX2021
High-Dynamic-Range, Direct Up-/Downconversion
650MHz to 1200MHz Quadrature Mod/Demod
Table 1. Typical Performance Trade-Offs as a Function of Current Draw—Modulator Mode
LO FREQ
(MHz)
800
900
1000
RF FREQ
(MHz)
801.8
901.8
1001.8
R1
( ? )
420
453
499
549
650
420
453
499
549
650
420
453
499
549
650
R2
( ? )
620
665
698
806
1000
620
665
698
806
1000
620
665
698
806
1000
R3
( ? )
330
360
402
464
550
330
360
402
464
550
330
360
402
464
550
I CC
(mA)
271
253
229
205
173
271
253
229
205
173
271
253
229
205
173
OIP3
(dBm)
19.6
21.9
18.9
15.7
13.6
20.7
21.6
20.6
19.0
14.9
22.4
22.2
19.9
17.6
14.6
LO LEAK
(dBm)
-32.1
-32.7
-33.7
-34.4
-34.2
-31.4
-31.6
-31.8
-31.9
-30.5
-32.8
-33.2
-33.8
-34.8
-33.9
IMAGE REJ
(dBc)
23.9
34.0
30.0
23.7
23.3
43.4
42.4
42.7
40.3
25.0
39.3
39.1
43.5
40.5
36.8
OIP2
(dBm)
50.5
51.0
52.6
46.0
32.3
54.0
55.4
59.8
50.7
34.6
55.5
56.3
55.0
51.4
32.8
Note: V CC = 5V, P LO = 0dBm, T A = +25°C, I/Q voltage levels = 1.4V P-P differential.
Power-Supply Bypassing
Proper voltage-supply bypassing is essential for high-
frequency circuit stability. Bypass all VCC_ pins with
33pF and 0.1μF capacitors placed as close to the pins
as possible. The smallest capacitor should be placed
closest to the device.
To achieve optimum performance, use good voltage-
supply layout techniques. The MAX2021 has several
RF processing stages that use the various VCC_
pins, and while they have on-chip decoupling, off-
chip interaction between them may degrade gain, lin-
earity, carrier suppression, and output power-control
range. Excessive coupling between stages may
degrade stability.
16
Exposed Pad RF/Thermal Considerations
The EP of the MAX2021’s 36-pin TQFN-EP package
provides a low thermal-resistance path to the die. It is
important that the PCB on which the IC is mounted be
designed to conduct heat from this contact. In addition,
the EP provides a low-inductance RF ground path for
the device.
The exposed pad (EP) MUST be soldered to a ground
plane on the PCB either directly or through an array of
plated via holes. An array of 9 vias, in a 3 x 3 array, is
suggested. Soldering the pad to ground is critical for
efficient heat transfer. Use a solid ground plane wher-
ever possible.
Maxim Integrated
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