参数资料
型号: MAX2057ETX+T
厂商: Maxim Integrated
文件页数: 11/13页
文件大小: 0K
描述: IC AMP VARIABLE GAIN 36-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 1.7GHz ~ 2.5GHz
P1dB: 23.8dBm(239.9mW)
增益: 13.5dB ~ 17.5dB
噪音数据: 6dB
RF 型: 手机,ATE,GSM,EDGE,ISM,W-CDMA,802.16/WiMax,CDMA2000
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 180mA ~ 230mA
测试频率: 2.1GHz
封装/外壳: 36-WFQFN 裸露焊盘
包装: 带卷 (TR)
1300MHz to 2700MHz Variable-Gain
Amplifier with Analog Gain Control
Table 1. Typical Application Circuit
Component Values
Amplifier Bias Current
The MAX2057 integrates a two-stage amplifier to simul-
taneously provide high gain and high IP3. Optimal per-
DESIGNATION
C1, C3, C5, C7, C10
C2, C4, C6, C8, C9
C13, C14, C15
C17
R1
R2
VALUE
22pF
1000pF
0.1μF
0.75pF
1.2k ?
2k ?
TYPE
Microwave capacitors
(0402)
Microwave capacitors
(0402)
Microwave capacitors
(0603)
Microwave capacitor
(0402)
±1% resistor (0402)
±1% resistor (0402)
formance is obtained when R1 and R2 are equal to
1.2k ? and 2k ? , respectively. The typical supply current
is 180mA and the typical output IP3 is 37dBm under
these conditions.
Increasing R 1 and R 2 from the nominal values of 1.2k ?
and 2k ? reduces the bias current of each amplifier
stage, which reduces the total power consumption and
IP3 of the device. This feature can be utilized to further
decrease power consumption for applications that do
not require high IP3.
Layout Considerations
A properly designed PC board is an essential part of
any RF/microwave circuit. Keep RF signal lines as short
as possible to reduce losses, radiation, and induc-
Applications Information
Analog Attenuation Control
A single input voltage at the V CNTL pin adjusts the gain
of the MAX2057. Up to 21dB of gain-control range is
provided through a single attenuator. At the maximum
gain setting, each attenuator’s insertion loss is approxi-
mately 2.2dB. With the single attenuator at the maximum
gain setting, the device provides a nominal 15.5dB of
cascaded gain and 6dB of cascaded noise figure.
If a larger gain-control range is desired, a second on-
chip attenuator can be connected in the signal path to
provide an additional 21dB of gain-control range. With
the second attenuator connected at the maximum gain
setting, the device typically exhibits 13.3dB of cascad-
ed gain. Note that the V CNTL pin simultaneously adjusts
both on-chip attenuators.
The V CNTL input voltage drives a high-impedance load
(> 50k ? ). It is suggested that a current-limiting resistor
be included in series with this connection to limit the
input current to less than 40mA should the control volt-
age be applied when V CC is not present. A series resis-
tor of greater than 200 ? will provide complete
protection for 5V control voltage ranges. Limit V CNTL
input voltages to a 1.0V to 4.5V range when V CC is
present to ensure the reliability of the device.
tance. For best performance, route the ground-pin
traces directly to the exposed pad underneath the
package. This pad MUST be connected to the ground
plane of the board by using multiple vias under the
device to provide the best RF and thermal conduction
path. Solder the exposed pad on the bottom of the
device package to a PC board exposed pad.
Power-Supply Bypassing
Proper voltage-supply bypassing is essential for high-
frequency circuit stability. Bypass each V CC pin with
capacitors placed as close to the device as possible.
Place the smallest capacitor closest to the device. Refer
to the MAX2057 evaluation kit data sheet for more details.
Exposed Pad RF and Thermal
Considerations
The EP of the MAX2057’s 36-pin thin QFN-EP package
provides a low-thermal-resistance path to the die. It is
important that the PC board on which the IC is mounted
be designed to conduct heat from this contact. In addi-
tion, the EP provides a low-inductance RF ground path
for the device.
The EP MUST be soldered to a ground plane on the PC
board either directly or through an array of plated via
holes. Soldering the pad to ground is also critical for
efficient heat transfer. Use a solid ground plane wher-
ever possible.
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