参数资料
型号: MAX2063ETM+T
厂商: Maxim Integrated
文件页数: 19/22页
文件大小: 0K
描述: IC VGA PROG DIGITAL 48TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 50MHz ~ 1GHz
P1dB: 18.8dB
增益: 18.3dB
噪音数据: 6.7dB
RF 型: 通用
电源电压: 3.135 V ~ 3.465 V,4.75 V ~ 5.25 V
电流 - 电源: 148mA
测试频率: 900MHz
封装/外壳: 48-WFQFN 裸露焊盘
包装: 带卷 (TR)
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
If desired, the user can also program two additional
attenuation states by using the STA_B_1 control bit as a
second I/O pin. These two additional attenuation settings
are useful for software-defined radio applications where
multiple static gain settings are needed to account for
different frequencies of operation, or where multiple
dynamic attenuation settings are needed to account for
different blocker levels (as defined by multiple wireless
standards).
Power-Supply Sequencing
The sequence to be used is:
1) Power supply
Layout Considerations
The pin configuration of the device is optimized to facili-
tate a very compact physical layout of the device and its
associated discrete components. The exposed pad (EP)
of the device’s 48-pin thin QFN-EP package provides a
low thermal-resistance path to the die. It is important that
the PCB on which the device is mounted be designed
to conduct heat from the EP. In addition, provide the EP
with a low inductance path to electrical ground. The EP
MUST be soldered to a ground plane on the PCB, either
directly or through an array of plated via holes.
Table 7 lists typical application circuit component values.
2)
Control lines
Table 4. Digital Attenuator Settings (Parallel Control, DA_SP = 0)
INPUT
D0_ _
D1_ _
D2_ _
D3_ _
D4_ _
LOGIC = 0 (OR GROUND)
Disable 1dB attenuator
Disable 2dB attenuator
Disable 4dB attenuator
Disable 8dB attenuator
Disable 16dB attenuator
LOGIC = 1
Enable 1dB attenuator
Enable 2dB attenuator
Enable 4dB attenuator
Enable 8dB attenuator
Enable 16dB attenuator
Table 5. Programme d Attenuation State Settings for Attenuator 1 (DA_SP = 1)
STA_A_1
0
1
0
1
STA_B_1
0
0
1
1
SETTING FOR DIGITAL ATTENUATOR 1*
Preprogrammed attenuation state 1
Preprogrammed attenuation state 2
Preprogrammed attenuation state 3
Preprogrammed attenuation state 4
*Defined by SPI programming bits D8:D27 (see Table 3 for details).
Table 6. Programme d Attenuation State Settings for Attenuator 2 (DA_SP = 1)
STA_A_2
0
1
0
1
STA_B_2
0
0
1
1
SETTING FOR DIGITAL ATTENUATOR 2*
Preprogrammed attenuation state 1
Preprogrammed attenuation state 2
Preprogrammed attenuation state 3
Preprogrammed attenuation state 4
*Defined by SPI programming bits D36:D55 (see Table 3 for details).
19
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