参数资料
型号: MAX2065ETL+T
厂商: Maxim Integrated
文件页数: 21/27页
文件大小: 0K
描述: IC A/D VGA 50MHZ-1000MHZ 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 50MHz ~ 1GHz
P1dB: 18.7dBm(74.1mW)
增益: 19.4db
噪音数据: 6.8dB
RF 型: 手机,CDMA,GSM
电源电压: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
电流 - 电源: 124mA
测试频率: 350MHz
封装/外壳: 40-WFQFN 裸露焊盘
包装: 带卷 (TR)
50MHz to 1000MHz High-Linearity, Serial/
Parallel-Controlled Analog/Digital VGA
Table 2. SPI Data Format (continued)
FUNCTION
On-Chip DAC
BIT
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DESCRIPTION
Bit 7 (MSB) of on-chip DAC used to program the analog attenuator
Bit 6 of DAC
Bit 5 of DAC
Bit 4 of DAC
Bit 3 of DAC
Bit 2 of DAC
Bit 1 of DAC
Bit 0 (LSB) of the on-chip DAC
Attenuator and DAC Operation
The analog attenuator is controlled by an external con-
trol voltage applied at ANALOG_VCTRL (pin 39) or by
the on-chip 8-bit DAC, while the digital attenuator is con-
trolled through the SPI-compatible interface or parallel
bus. The DAC enable/disable logic-input pin
(VDAC_EN), digital attenuator SPI or parallel control
selection logic-input pin (SER/PAR), and the DAC refer-
ence voltage selection logic-input pin (VREF_SELECT)
determine how the attenuators are controlled. The on-
chip DAC can also be enabled or disabled. When the
DAC is enabled, either the on-chip voltage reference or
the external voltage reference can be selected. See
Table 1 for the attenuator and DAC operation truth table.
Digital Attenuator Settings
Using the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the
MAX2065 offers a supplemental 5-bit parallel control
interface. The digital logic attenuator-control pins
(D0–D4) enable the attenuator stages (Table 3).
Direct access to this 5-bit bus enables the user to avoid
any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states needed for critical “fast-attack”
automatic gain control (AGC) applications.
“Rapid-Fire” Preprogrammed
Attenuation States
The MAX2065 has an added feature that provides
“rapid fire ” gain selection between four prepro-
grammed attenuation steps. As with the supplemental
5-bit bus mentioned above, this “rapid fire” gain selec-
tion allows the user to quickly access any one of four
customized digital attenuation states without incurring
the delays associated with reprogramming the device
through the SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel bus. However, by
employing this specific feature, the digital attenuator
I/O is further reduced by a factor of either 5 or 2.5 (5
control bits vs. 1 or 2, respectively) depending on the
number of states desired.
Table 3. Digital Attenuator Settings (Parallel Control)
INPUT
D0
D1
D2
D3
D4
LOGIC = 0 (OR GROUND)
Disable 1dB attenuator, or when SPI is default programmer
Disable 2dB attenuator, or when SPI is default programmer
Disable 4dB attenuator, or when SPI is default programmer
Disable 8dB attenuator, or when SPI is default programmer
Disable 16dB attenuator, or when SPI is default programmer
LOGIC = 1
Enable 1dB attenuator
Enable 2dB attenuator
Enable 4dB attenuator
Enable 8dB attenuator
Enable 16dB attenuator
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