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参数资料
| 型号： | MAX2235EUP+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC AMP POWER 900MHZ 20TSSOP |
| 标准包装： | 2,500 |
| 频率： | 801 ~ 1000MHz |
| 增益： | 26dB |
| RF 型： | ISM |
| 电源电压： | 2.7V ~ 5.5V |
| 电流 - 电源： | 610mA |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
+3.6V, 1W Autoramping Power
Amplifier for 900MHz Applications
Typical Operating Characteristics (continued)
(MAX2235 Evaluation Kit, GC = unconnected, f RFIN = 836MHz, V CC = V SHDN = +3.6V, T A = +25°C, unless otherwise noted.)
1400
RISE TIME vs. RAMPING CAPACITANCE
1200
FALL TIME vs. RAMPING CAPACITANCE
1200
1000
FULL POWER = +10dBm
FULL POWER = +20dBm
1000
800
FULL POWER = +30dBm
FULL POWER = +10dBm
800
600
600
400
400
200
FULL POWER = +30dBm
200
FULL POWER = +20dBm
0
0
20
40
60
80
100
120
0
0
20
40
60
80
100
120
CAPACITANCE (nF)
CAPACITANCE (nF)
Pin Description
PIN
1
2
3
4
5
6, 7, 10
8
9
11
12
13, 14,
17, 18,
SLUG
15
16
19
20
NAME
RFIN
GND
V CC
V CC
V CC
GND
V CC
V CC
RAMP
REF
GND
RFOUT
RFOUT
SHDN
GC
FUNCTION
RF Input. A DC blocking capacitor in series with RFIN is required. The value of the capacitor depends on
the operating frequency.
GND connection for the input stage (variable-gain amplifier). Connect to the circuit board ground plane
with a separate low-inductance path (via).
Supply Voltage Input for the Input Stage. Bypass with its own 100pF low-inductance capacitor to GND.
Supply Voltage Input for Bias Circuitry. Bypass with its own 100pF low-inductance capacitor and a 1000pF
capacitor to GND, to minimize RF signal coupling into the bias circuits.
Supply Voltage Input for the Input Stage. Bypass with its own 22pF low-inductance capacitor to pins 6 and 7.
GND Connection for the Second-Stage Amplifier (driver). Connect to the circuit board ground plane with a
separate low-inductance path (via).
Supply Voltage Input for the Second Stage. Bypass with its own 220pF and 1000pF low-inductance
capacitors to GND.
Supply Voltage Input for the Second Stage. Connect to pin 8.
Power Ramp Pin. Connect a capacitor between RAMP and REF to provide a gradual linear power-up/down
ramp. See Detailed Description .
Reference Voltage for RAMP Capacitor. The reference is internally set to 1.9V.
GND Connection for the Power Stage. Solder the slug to the circuit board ground plane. Connect pins 13,
14, 17, and 18 to the slug with a straight board trace under the chip.
Power Amplifier Output. See Typical Operating Circuit for an example of a matching network, which pro-
vides optimal output power at 836MHz. Connect to pin 16.
Power Amplifier Output. Connect to pin 15.
Shutdown Pin. Drive SHDN low to turn the device off. Drive above 2.0V to turn the device on. Drive V SHDN
> 2.0V and V GC < 0.4V for standby mode.
Gain-Control Pin. Apply V GC between 0.6V and 2.3V to control the output power with a monotonic dB/V
relationship. See the Typical Operating Characteristics for a typical relationship.
_______________________________________________________________________________________
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