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参数资料
| 型号： | MAX2310-MAX2316 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quad 2-input positive-NAND buffers with open collector outputs 14-SOIC 0 to 70 |
| 中文描述： | 码分多址中的IF VGA和I / VCO及合成器Q解调器 |
| 文件页数： | 14/22页 |
| 文件大小： | 342K |
| 代理商： | MAX2310-MAX2316 |
M
B
M
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
14
______________________________________________________________________________________
the VGC pin. The output of the VGA drives the RF ports
of a quadrature demodulator. The MAX2310/MAX2314
provide two types of FM demodulation, controlled by
the FM_TYPE (FT) control bit. When FM_TYPE is “1,”
the signal is passed through both the I and Q signal
paths for subsequent lowpass filtering and A/D conver-
sion at baseband. If FM_TYPE is “0,” the FM signal is
passed through the I mixer only.
Voltage-Controlled Oscillator,
Buffers, and Quadrature Generation
The LO signal for downconversion is provided by a
voltage-controlled oscillator (VCO) consisting of an on-
chip differential oscillator, and an off-chip high-Q reso-
nant network. Figure 4 shows a simplified schematic of
the VCO oscillator. Multiband operation is supported by
the MAX2310 with dual VCOs. VCO_H and VCO_L are
selectable with the MODE pin or the VCO_SEL (VS)
control bit. They oscillate at twice the desired LO fre-
quency. For applications requiring an external LO, the
VCOs can be bypassed with the VCO_BYP (VB) control
bit.
The MAX2312/MAX2316 buffer the output of the VCO
and provide this signal at the LOOUT pin. This signal is
enabled by the
BUFEN
(BE) control bit or by the
BUFEN
control pin. The frequency of this signal is
selected by the BUF_DIV (BD) control bit, and can be
either the VCO frequency or half the VCO frequency.
Quadrature downconversion is realized by providing in-
phase (I) and quadrature-phase (Q) components of the
LO signal to the LO ports of the demodulator described
above. The quadrature LO signals are generated by
dividing the VCO output frequency using two latches.
The appropriate latch outputs provide I and Q signals
at the desired LO frequency.
Table 3. MAX2314 Control Register States
Note:
H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter
S
OPERATIONAL
MODE
1
1
1
0
X
X
0
FM_I
FM I operation
0
H
1
0
1
0
X
X
0
FM_IQ
FM IQ quadrature operation
0
H
1
X
1
1
X
X
0
CDMA
CDMA operation
0
H
0
1
X
X
0
STANDBY
0 in standby pin turns off VGA and
modulator only
0
H
X
X
L
X
X
X
X
X
X
SHUTDOWN
0 in shutdown register bit leaves seri-
al port active
X
H
X
X
X
X
X
X
M
S
B
L
S
B
CONTROL REGISTER
S
X
I
F
X
X
B
B
X
X
X
V
V
SHUTDOWN
Shutdown pin completely shuts down
chip
D
X
L
X
X
T
T
X
C
P
I
N
S
T
ACTION
RESULT
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