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参数资料
| 型号： | MAX2741ETI |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 运动控制电子 |
| 英文描述： | Integrated L1-Band GPS Receiver |
| 中文描述： | SWITCHED CAPACITOR FILTER, BESSEL, BANDPASS, QCC28 |
| 封装： | 5 X 5 MM, 0.80 MM HEIGHT, MO-220-WHHD, TQFN-28 |
| 文件页数： | 5/12页 |
| 文件大小： | 239K |
| 代理商： | MAX2741ETI |
M
Integrated L1-Band GPS Receiver
_______________________________________________________________________________________
5
Detailed Description
The MAX2741 GPS offers a high-performance super-
heterodyne receiver solution for low-power mobile
devices, with the benefit of using the system’s existing
clock reference. This receiver is ideal for integration into
mobile phone handsets using common reference fre-
quencies such as 10.0, 13.0, 14.4, 19.2, 20.0, and
26.0MHz. The only external components required are the
GPS RF filter, an IF filter (typically designed from inexpen-
sive discretes), a three-component PLL loop filter, and a
few other resistors and capacitors. The MAX2741 inte-
grates the reference oscillator core, the VCO and its tank,
the synthesizer, a 1- to 3-bit ADC, and all signal path
blocks except for the 1st IF filter. The typical application
area for the receiver is less than 2cm
2
.
RF/1st Conversion Stage (Front-End)
The MAX2741 RF front-end LNA and mixer are the most
important in the signal path. This stage sets the noise
figure for the receiver, defining the sensitivity, and mixes
the 1575.42MHz L1-band GPS signal down to a 1st IF of
37.38MHz. The LNA itself has an NF of approximately
1.5dB; the cascaded NF of the front-end (including the
mixer) is approximately 4.7dB, and the cascaded gain
is typically 21dB.
The image-reject mixer is set up for a high-side injected
RFLO (1612.80MHz), and offers typically better than 30dB
rejection of the image noise (1650.18MHz). The -30dBm
input 3rd-order intercept (IIP3) of the RF strip, in conjunc-
tion with the GPS IF filter, provides excellent out-of-band
interferer immunity.
The 1st IF outputs (IFOUT±) are internally biased to
approximately 2V, and have a differential source
impedance of approximately 2.5k
. The IF filter can be
implemented as a discrete L/C filter, or as a monolithic
SAW or ceramic if one is available.
IF/2nd Conversion Stage
The 2nd conversion stage consists of an active mixer, a
variable-gain amplifier (VGA), and a tunable lowpass
filter. The IF mixer is configured for low-side LO injec-
tion for a 2nd IF of 3.78MHz. Total gain in this stage is
62dB, and the VGA offers 51dB of gain adjustment. The
VGA is typically controlled by the baseband IC through
the SPI interface to optimize the signal swing for digiti-
zation by the ADC.
The on-chip lowpass filter has an adjustable cutoff fre-
quency, programmable from 2.9MHz to 7.7MHz in 16
steps. This LPF further reduces out-of-band noise and
band-limits the signal to the ADC, ensuring that the
sampling process does not generate alias components.
DC offset compensation at the ADC input is performed by
an on-chip 4-bit DAC. This compensates for any DC error
introduced by transistor mismatch in the differential stage
driving the ADC input, allowing the downconverted GPS
signal’s DC level to be centered within the threshold volt-
ages of the ADC.
ADC
The on-chip ADC samples the down-converted GPS
signal at the 2nd IF (3.78MHz). Sampled output is pro-
vided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit
(2-bit magnitude, 1-bit sign) formats, as determined by
the ADC mode configuration bit (CONFIG1:D15); see
Table 5 for details. The ADC sample clock (system GPS
clock) is derived either directly from the reference clock
(SYNTH:D9 = 1), or from an RFLO divide-by-96 block to
provide a 16.8MHz sample clock (SYNTH:D9 = 0). The
clock is available to the baseband processor at
GPSCLK (pin 15). The sampled ADC data bits are
available on pins 16, 17, and 18 (GPSIF2, GPSIF1, and
GPSIF0). The functionality of the pins is different in
each mode (2-bit vs. 3-bit)—see Table 5 in determining
the interface connection for the application circuit.
Synthesizer
The MAX2741 integrates an integer-N synthesizer; all
blocks except the loop filter are on-chip. The reference
can be either a crystal (driven by the internal oscillator),
or a TCXO module. The oscillator provides a 5pF load
to the crystal. A TCXO module should provide a swing
in the 0.6V
P-P
to 2.2V
P-P
range.
The reference divider (/R) is programmable (SYNTH:
D7–D0), and can accommodate reference frequencies
up to 26MHz. The reference divider needs to be set so
the comparison frequency (f
COMP
) at the frequency/
phase detector is 200kHz. The VCO runs at twice the fre-
quency of the RFLO; the RFLO is therefore generated
from the VCO using a quadrature divide-by-2 block. The
RF LO is f
COMP
x 8064 (typically 1612.80MHz), and the
1st IF LO is f
COMP
x 168 (typically 33.6MHz); the RF and
IF LO division ratios are not adjustable. This configuration
allows for the use of reference frequencies common to
GSM, CDMA, TDMA, TD-SCDMA, and UMTS handsets:
9.6MHz (R = 48), 13.0MHz (R = 65), 14.4MHz (R = 72),
19.2MHz (R = 96), 26.0MHz (R = 130), etc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX2741ETI+ | 功能描述:射频接收器 Integrated L1-Band GPS Receiver RoHS:否 制造商:Skyworks Solutions, Inc. 类型:GPS Receiver 封装 / 箱体:QFN-24 工作频率:4.092 MHz 工作电源电压:3.3 V 封装:Reel |
| MAX2741ETI+T | 功能描述:射频接收器 Integrated L1-Band GPS Receiver RoHS:否 制造商:Skyworks Solutions, Inc. 类型:GPS Receiver 封装 / 箱体:QFN-24 工作频率:4.092 MHz 工作电源电压:3.3 V 封装:Reel |
| MAX2741ETI-T | 功能描述:射频接收器 RoHS:否 制造商:Skyworks Solutions, Inc. 类型:GPS Receiver 封装 / 箱体:QFN-24 工作频率:4.092 MHz 工作电源电压:3.3 V 封装:Reel |
| MAX2741EVKIT | 功能描述:GPS开发工具 MAX2741 Eval Kit RoHS:否 制造商:STMicroelectronics 产品:Evaluation Boards 工具用于评估:IT600, STM32F20x 频率:1.575 GHz 工作电源电压:1.8 V 接口类型:Wireless |
| MAX2741USBDONGLE | 制造商:Maxim Integrated Products 功能描述: |
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