参数资料
型号: MAX2839ASEWO+T
厂商: Maxim Integrated
文件页数: 20/39页
文件大小: 0K
描述: IC TXRX MIMO 2.3GHZ-2.7GHZ 73WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 2.3GHz ~ 2.7GHz
调制或协议: 802.16,802.11b/g
应用: MIMO,WLAN
功率 - 输出: 0dBm
电源电压: 2.7 V ~ 3.6 V
电流 - 接收: 120mA
电流 - 传输: 145mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 73-WLP
包装: 带卷 (TR)
2.3GHz to 2.7GHz MIMO Wireless
Broadband RF Transceiver
Bump Description (continued)
BUMP
39
40
41
42
43
44
45
46
47
48
49
50
51
52, 67
53
NAME
GNDRXLNA_B
RXINB-
TXRX
B5
TXOUT+
B1
TXOUT-
V CCTXMX
CLKOUT
GND_XTAL
GND_DIG
V CC_DIG
CPOUT-
GND
DIN
FUNCTION
Receiver B LNA Ground
Receiver B LNA Differential Input Minus. Input is internally DC-coupled.
Transmit/Receive Mode Enable Logic Input
Receiver and Transmitter Gain-Control Logic Input Bit 5
Power Amplifier Driver Differential Output Plus. The pin is biased at V CC /2 internally.
Receiver and Transmitter Gain-Control Logic Input Bit 1
Power Amplifier Driver Differential Output Minus. The pin is biased at V CC /2 internally.
Transmitter Upconverter Supply Voltage. Bypass with a 22pF capacitor as close as possible to the
pin.
Reference Clock Buffer Output
Crystal Oscillator Ground
PLL Digital Ground
PLL Digital Supply Voltage. Bypass with a 100nF capacitor as close as possible to the pin.
Differential Charge-Pump Output Minus. Connect the frequency synthesizer’s loop filter between
CPOUT+ and CPOUT- (see the Typical Operating Circuit ).
Ground. Connect to the PCB ground plane.
Data Logic Input of 4-Wire Serial Interface
54
GND_PAD_BIAS Transmit Bias Ground
55
56
57
58
59
60
61
62
63
64
65
66
68
69
70
71
72
73
XTAL1
RXHP
RXBBIA-
RXBBIA+
TXBBI+
TXBBQ+
V CCRXMX
RXINA-
RXINA+
B0
ENABLE
DOUT
RXBBIB-
RXBBQB-
RSSI
B7
V CCRXFL
TXBBI-
XTAL Input. AC-couple crystal to this analog pin.
Receiver I- and Q-Channel AC-Coupling Highpass Corner Frequency Selection Logic Input
Receiver A Baseband I-Channel Differential Output Minus
Receiver A Baseband I-Channel Differential Output Plus
Transmitter Baseband I-Channel Differential Input Plus
Transmitter Baseband Q-Channel Differential Input Plus
Receiver Downconverters Supply Voltage. Bypass with a 22pF capacitor as close as possible to the
pin.
Receiver A LNA Differential Input Minus. Input is internally DC-coupled.
Receiver A LNA Differential Input Plus. Input is internally DC-coupled.
Receiver and Transmitter Gain-Control Logic Input Bit 0
Transceiver Enable Logic Input
Data Logic Output of 4-Wire Serial Interface
Receiver B Baseband I-Channel Differential Output Minus
Receiver B Baseband Q-Channel Differential Output Minus
Receiver Signal Strength Output
Receiver Gain-Control Logic Input Bit 7
Receiver Baseband Filter Supply Voltage. Bypass with a 100nF capacitor as close as possible to
the pin.
Transmitter Baseband I-Channel Differential Input Minus
20
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