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参数资料
| 型号： | MAX2839ETN+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 18/26页 |
| 文件大小： | 0K |
| 描述： | IC TXRX MIMO 2.3-2.7GHZ 56TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 2.3GHz ~ 2.7GHz |
| 调制或协议： | 802.16，802.11b/g |
| 应用： | MIMO，WLAN |
| 功率 - 输出： | 0dBm |
| 电源电压： | 2.7 V ~ 3.6 V |
| 电流 - 接收： | 117mA |
| 电流 - 传输： | 140mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 56-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
2.3GHz to 2.7GHz MIMO Wireless Broadband
RF Transceiver
Pin Description
PIN
NAME
FUNCTION
1
2
GNDRXLNA_A Receiver A LNA Ground
VCCRXLNA_A Receiver A LNA Supply Voltage. Bypass with a 22pF capacitor as close as possible to the pin.
3
4
B0
LOAD
Receiver Gain-Control Logic Input Bit 0
Receiver Gain Select. Positive edge trigger latches digital gain inputs B0–B7 to receive A. Negative
edge trigger latches digital gain inputs B0–B7 to receive B.
5
6
VCCRXLNA_B Receiver B LNA Supply Voltage. Bypass with a 22pF capacitor as close as possible to the pin.
GNDRXLNA_B Receiver B LNA Ground
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
RXINB+
RXINB-
B4
B3
VCCTXPAD
B2
TXOUT+
TXOUT-
B1
B5
PABIAS
VCCTXMX
SCLK
ENABLE
CLKOUT
REFCLK
XTAL1
VCCXTAL
VCCCP
GNDCP
CPOUT+
CPOUT-
GNDVCO
VCOBYP
VCCVCO
CS
DOUT
DIN
RXBBIB-
RXBBIB+
RXBBQB-
RXBBQB+
Receiver B LNA Differential Input. Input is internally DC-coupled.
Receiver and Transmitter Gain-Control Logic Input Bit 4
Receiver and Transmitter Gain-Control Logic Input Bit 3
Supply Voltage for Transmitter PA Driver. Bypass with a 22pF capacitor as close as possible to the pin.
Receiver and Transmitter Gain-Control Logic Input Bit 2
Power Amplifier Driver Differential Output. The pins have internal AC blocking capacitors.
Receiver and Transmitter Gain-Control Logic Input Bit 1
Receiver and Transmitter Gain-Control Logic Input Bit 5
Transmit External PA Bias DAC Output
Transmitter Upconverter Supply Voltage. Bypass with a 22pF capacitor as close as possible to the pin.
Serial-Clock Logic Input of 4-Wire Serial Interface
Transceiver Enable
Reference Clock Buffer Output
Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.
XTAL Input. Connect the other terminal of the XTAL to this pin.
Crystal Oscillator Supply Voltage. Bypass with a 100nF capacitor as close as possible to the pin.
PLL Charge-Pump Supply Voltage. Bypass with a 100nF capacitor as close as possible to the pin.
Charge-Pump Circuit Ground
Differential Charge-Pump Output. Connect the frequency synthesizer’s loop filter between these pins
(see the Typical Operating Circuit ).
VCO Ground
On-Chip VCO Regulator Output Bypass. Bypass with a 1μF capacitor to GND. Do not connect other
circuitry to this pin.
VCO Supply Voltage. Bypass with a 22nF capacitor as close as possible to the pin.
Chip-Select Logic Input of 4-Wire Serial Interface
Data Logic Output of 4-Wire Serial Interface
Data Logic Input of 4-Wire Serial Interface
Receiver B Baseband I-Channel Differential Outputs
Receiver B Baseband Q-Channel Differential Outputs
18
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