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参数资料
| 型号： | MAX3140EEI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 33/36页 |
| 文件大小： | 0K |
| 描述： | IC UART W/RS485 28-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 特点： | 收发器 |
| FIFO's： | 8 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-QSOP |
| 供应商设备封装： | 28-QSOP |
| 包装： | 带卷 (TR) |
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MAX3140
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
6
_______________________________________________________________________________________
SWITCHING CHARACTERISTICS—SRL = VCC
(VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.)
250
720
1000
Receiver Enable from Shutdown
to Output Low
tRZL(SHDN)
3500
ns
Figures 2 and 8, CL = 100pF, S1 closed
tDPHL
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Driver Disable Time from Low
tDLZ
100
ns
Driver Enable to Output Low
tDZL
2500
ns
Driver Enable to Output High
tDZH
2500
ns
Maximum Data Rate
fMAX
500
kbps
Driver Disable Time from High
tDHZ
100
ns
Receiver Input to Output
tRPLH,
tRPHL
127
200
ns
|tRPLH - tRPHL| Differential
Receiver Skew
tRSKD
3±30
ns
Receiver Enable to Output Low
tRZL
20
50
ns
Driver Output Skew
|tDPLH - tDPHL|
Driver Input to Output
tDPLH
250
720
1000
ns
tDSKEW
-3
±100
ns
Driver Rise or Fall Time
tDR, tDF
200
530
950
ns
Receiver Enable to Output High
tRZH
20
50
ns
Receiver Disable Time from Low
tRLZ
20
50
ns
Receiver Disable Time from
High
tRHZ
20
50
ns
Time to Shutdown
tSHDN
50
200
600
ns
Driver Enable from Shutdown to
Output High
tDZH(SHDN)
4500
ns
Driver Enable from Shutdown to
Output Low
tDZL(SHDN)
4500
ns
Receiver Enable from Shutdown
to Output High
tRZH(SHDN)
3500
ns
CONDITIONS
Figures 2 and 8, CL = 100pF, S2 closed
Figures 4 and 6, CL = 15pF, S1 closed
Figures 2 and 8, CL = 100pF, S1 closed
Figures 4 and 6, CL = 100pF, S1 closed
Figures 4 and 6, CL = 100pF, S2 closed
Figures 4 and 6, CL = 15pF, S2 closed
Figures 7 and 9,
|VID| ≥ 2.0V,
rise and fall time of VID
≤ 15ns
Figures 2 and 8, CL = 100pF, S2 closed
(Note 5)
Figures 7 and 9,
|VID| ≥ 2.0V,
rise and fall time of VID
≤ 15ns
Figures 2 and 8, CL = 100pF, S1 closed
Figures 4 and 6, CL = 15pF, S2 closed
Figures 4 and 6, CL = 15pF, S1 closed
Figures 2 and 8, CL = 100pF, S2 closed
Figures 3 and 5, RDIFF = 54
Ω,
CL1 = CL2 = 100pF
Figures 3 and 5, RDIFF = 54
Ω,
CL1 = CL2 = 100pF
Figures 3 and 5, RDIFF = 54
Ω,
CL1 = CL2 = 100pF
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