参数资料
型号: MAX3203EEBT+T
厂商: Maxim Integrated Products
文件页数: 5/9页
文件大小: 0K
描述: IC ESD PROT ARRAY 5-UCSP
标准包装: 2,500
电极标记: 3 通道阵列 - 单向
安装类型: 表面贴装
封装/外壳: 5-WFBGA,CSPBGA
供应商设备封装: 5-UCSP(1.52x1.05)
包装: 带卷 (TR)
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a 15kV IEC-61000 Air-Gap Discharge ESD event,
the pulse current rises to approximately 45A in 1ns
(di/dt = 45 x 10 9 ). An inductance of only 10nH adds an
additional 450V to the clamp voltage. An inductance of
10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1μF capacitor must be used between V CC
and GND. This bypass capacitor absorbs the charge
transferred by an +8kV IEC-61000 Contact Discharge
ESD event.
Ideally, the supply rail (V CC ) would absorb the charge
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
? ±15kV using the Human Body Model
? ±8kV using the Contact Discharge method speci-
fied in IEC 61000-4-2
? ±15kV using the IEC 61000-4-2 Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
Human Body Model
Figure 4 shows the Human Body Model, and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5k ? resistor.
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1 ? , then
by using V = I × R, the clamping voltage of V C increas-
es by the equation V C = I ESD x R OUT . An +8kV IEC
61000-4-2 ESD event generates a current spike of 24A,
so the clamping voltage increases by V C = 24A × 1 ? ,
R C
1M ?
CHARGE-CURRENT-
LIMIT RESISTOR
R D
1.5k ?
DISCHARGE
RESISTANCE
or V C = 24V. Again, a poor layout without proper
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX3202E/
HIGH-
VOLTAGE
DC
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
MAX3203E/MAX3204E/MAX3206E V CC pin is the best
choice for this application. A bypass capacitor should
also be placed as close to the protected device as
possible.
±15kV ESD Protection
ESD protection can be tested in various ways; the
MAX3202E/MAX3203E/MAX3204E/MAX3206E are
characterized for protection to the following limits:
I
SOURCE
Figure 4. Human Body ESD Test Model
100%
90%
I P 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
10%
0
t R = 0.7ns to 1ns
30ns
t
0
t RL
TIME
t DL
60ns
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
CURRENT WAVEFORM
Figure 5. Human Body Model Current Waveform
_______________________________________________________________________________________
5
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