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| 型号： | MAX3204EEWT+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/9页 |
| 文件大小： | 0K |
| 描述： | IC ESD PROT ARRAY 4CH 6WLP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 电极标记： | 4 通道阵列 - 单向 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFBGA，WLPBGA |
| 供应商设备封装： | 6-WLP（1.57x1.05） |
| 包装： | 带卷 (TR) |
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
The Air-Gap Discharge test involves approaching the
R C
50 ? to 100 ?
CHARGE-CURRENT-
LIMIT RESISTOR
R D
330 ?
DISCHARGE
RESISTANCE
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
Layout Recommendations
Proper circuit-board layout is critical to suppress ESD-
HIGH-
VOLTAGE
DC
SOURCE
Cs
150pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
induced line transients. The MAX3202E/MAX3203E/
MAX3204E/MAX3206E clamp to 100V; however, with
improper layout, the voltage spike at the device is
much higher. A lead inductance of 10nH with a 45A
current spike at a dv/dt of 1ns results in an ADDITION-
AL 450V spike on the protected line. It is essential that
the layout of the PC board follows these guidelines:
1) Minimize trace length between the connector or
Figure 6. IEC 61000-4-2 ESD Test Model
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. The MAX3202E/
MAX3203E/MAX3204E/MAX3206E help users design
equipment that meets Level 4 of IEC 61000-4-2.
The main difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2. Because series resistance is
lower in the IEC 61000-4-2 ESD test model (Figure 6)
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 3 shows the current waveform for
the ±8kV IEC 61000-4-2 Level 4 ESD Contact
Discharge test.
input terminal, I/O_, and the protected signal line.
2) Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.
3) Ensure short ESD transient return paths to GND
and V CC .
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
PC board.
6) Bypass V CC to GND with a low-ESR ceramic capac-
itor as close to V CC as possible.
7) Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close to the
supply pin as possible.
6
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