参数资料
型号: MAX3208EAUB+T
厂商: Maxim Integrated Products
文件页数: 5/9页
文件大小: 0K
描述: IC ESD PROT DIFF 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
电极标记: 4 通道阵列 - 单向
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-µMAX
包装: 带卷 (TR)
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section). A good layout reduces the parasitic series
inductance on the ground line, supply line, and protect-
ed signal lines. The MAX3205E/MAX3207E/MAX3208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
V CC . In an ideal circuit, the clamping voltage (V C ) is
defined as the forward voltage drop (V F ) of the protec-
tion diode, plus any supply voltage present on the cath-
ode.
For positive ESD pulses:
V C = V CC + V F
For negative ESD pulses:
V C = -V F
The effect of the parasitic series inductance on the
lines must also be considered (Figure 1).
For positive ESD pulses:
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 2). For example,
in a 15kV IEC 61000 Air-Gap Discharge ESD event, the
pulse current rises to approximately 45A in 1ns (di/dt =
45 x 10 9 ). An inductance of only 10nH adds an addi-
tional 450V to the clamp voltage and represents
approximately 0.5in of board trace. Regardless of the
device’s specified diode clamp voltage, a poor layout
with parasitic inductance significantly increases the
effective clamp voltage at the protected signal line.
Minimize the effects of parasitic inductance by placing
the MAX3205E/MAX3207E/MAX3208E as close to the
connector (or ESD contact point) as possible.
A low-ESR 0.1μF capacitor is recommended between
V CC and GND in order to get the maximum ESD protec-
tion possible. This bypass capacitor absorbs the
charge transferred by a positive ESD event. Ideally, the
supply rail (V CC ) would absorb the charge caused by a
positive ESD strike without changing its regulated
value. All power supplies have an effective output
impedance on their positive rails. If a power supply’s
effective output impedance is 1 Ω , then by using V = I x
R, the clamping voltage of V C increases by the equa-
V C CC F ( D 1 ) + ? L 1 x
= V
+ V
? + ? L 2 x
d ( I ESD ) ? ? d ( I ESD ) ?
? ?
?
?
?
?
For negative ESD pulses:
dt dt
tion V C = I ESD x R OUT . A +8kV IEC 61000-4-2 ESD
event generates a current spike of 24A. The clamping
voltage increases by V C = 24A x 1 Ω , or V C = 24V.
Again, a poor layout without proper bypassing increas-
es the clamping voltage. A ceramic chip capacitor
V C = ? ? V F ( D 2 ) + ? L 1 x
? + ? L 3 x
? ?
? ?
? ?
d ( I ESD ) ? ? d ( I ESD ) ? ?
dt ? ? dt ? ?
mounted as close as possible to the MAX3205E/
MAX3207E/MAX3208E V CC pin is the best choice for
this application. A bypass capacitor should also be
placed as close to the protected device as possible.
where I ESD is the ESD current pulse.
POSITIVE SUPPLY RAIL
I
L2
100%
90%
D1
L1
I/O_
PROTECTED
LINE
D2
10%
L3
t R = 0.7ns to 1ns
30ns
60ns
t
GROUND RAIL
Figure 1. Parasitic Series Inductance
Figure 2. IEC 61000-4-2 ESD Generator Current Waveform
_______________________________________________________________________________________
5
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