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| 型号： | MAX3269CUB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/17页 |
| 文件大小： | 0K |
| 描述： | IC AMP LIMITING 1.25GBPS 10-UMAX |
| 标准包装： | 2,500 |
| 类型： | 限幅放大器 |
| 应用： | 光纤学网络 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 10-µMAX-EP |
| 包装： | 带卷 (TR) |
MAX3264/MAX3265/MAX3268/MAX3269/MAX3765/MAX3768
+3.0V to +5.5V, 1.25Gbps/2.5Gbps
Limiting Amplifiers
12
______________________________________________________________________________________
The buffer’s output impedance is determined by the par-
allel combination of internal and external pullup resistors,
which are chosen to match the impedance of the trans-
mission line (Figure 1). The output buffer can be AC- or
DC-coupled to the load.
PECL Output Buffer
The MAX3268/MAX3269/MAX3768 offer an industry-
standard PECL output. The PECL outputs should be
terminated to VCC - 2V. Figure 6 shows the PECL out-
put circuit. The squelch function forces OUT+ to a high
level and OUT- to a low level when the input is below
the programmed LOS threshold. In the 10-pin MAX,
SQUELCH is left unconnected.
__________________Design Procedure
Program the LOS Assert Threshold
The loss-of-signal threshold is programmed by external
resistor RTH. See the LOS Threshold vs. RTH graph in
the Typical Operating Characteristics.
Select the Coupling Capacitors
The coupling capacitors (CIN, COUT) should be select-
ed to minimize the receiver’s deterministic jitter. Jitter is
minimized when the input low-frequency cutoff (fIN) is
placed at a low frequency:
fIN = 1 / [2π(50)(C)]
For Fibre Channel, Gigabit Ethernet, or other applica-
tions using 8B/10B data coding, select (CIN, COUT) ≥
0.01F, which provides fIN < 320kHz. For ATM/SONET
or other applications using scrambled NRZ data, select
(CIN,COUT) ≥ 0.1F, which provides fIN < 32kHz.
Select the Offset-Correction Capacitor
(MAX3264/MAX3265 TSSOP Only)
To maintain stability, it is important to keep a one-
decade separation between fIN and the low-frequency
cutoff (fOC) associated with the DC-offset-correction cir-
cuit.
fOC = 75 / [2π 60k (CAZ + 100pF)]
= 200 x 10 -6 / (CAZ + 100pF)
For Fibre Channel, Gigabit Ethernet, or other applica-
tions using 8B/10B data coding, leave pins CAZ1, and
CAZ2 open (fOC = 2MHz). For ATM/SONET or other
applications using scrambled NRZ data, select CAZ ≥
0.1F, which typically provides fOC = 2kHz.
GND
ESD
STRUCTURES
VCC
OUT-
OUT+
Figure 6. PECL Output Circuit
GND
LEVEL
ESD
STRUCTURES
VCC
100
OUT-
OUT+
Figure 7. CML Output Circuit
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相关代理商/技术参数 |
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| MAX326C/D | 功能描述:模拟开关 IC Quad SPST Ultra-Low-Leakage CMOS Analog Switches RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
| MAX326CEE | 功能描述:模拟开关 IC RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
| MAX326CEE+ | 功能描述:模拟开关 IC Quad SPST CMOS Ultra-Low-Leakage RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
| MAX326CEE+T | 功能描述:模拟开关 IC Quad SPST CMOS Ultra-Low-Leakage RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
| MAX326CEE-T | 功能描述:模拟开关 IC RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
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