参数资料
型号: MAX3353EEUE+T
厂商: Maxim Integrated Products
文件页数: 13/21页
文件大小: 0K
描述: IC CHARGE PUMP USB OTG 16TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 充电泵,USB
输入电压: 2.6 V ~ 5.5 V
输出数: 2
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
USB On-the-Go Charge Pump with Switchable
Pullup/Pulldown Resistors
Table 1. MAX3353E Address Map
Interrupt Registers (14h, 15h, 16h)
There are three interrupt registers. Interrupt mask regis-
ADD PIN
Float or
GND
A 6
0
A 5
1
ADDRESS BITS
A 4 A 3 A 2
0 1 1
A 1
0
A 0
0
ter is a read/write register used to enable interrupts and
read status of interrupts. Interrupt edge register is a
read/write register for setting and determining inter-
rupts for positive and negative edges. Interrupt latch
register is a read only register to check and validate
V L
0
1
0
1
1
0
1
interrupt requests. Table 8 shows the interrupt mask,
Table 2. Register Address Map
NAME
Manufacturer
Register 0
Manufacturer
Register 1
Manufacturer
Register 2
Manufacturer
Register 3
Product ID
Register 0
Product ID
Register 1
Product ID
Register 2
Product ID
Register 3
Reserved
Control
Register 1
ADD
00h
01h
02h
03h
04h
05h
06h
07h
08h-0Fh
10h
BIT 7
0
0
0
0
0
0
0
0
DM_
PULLDWN
BIT 6
1
0
1
0
1
1
1
0
DP_
PULLDWN
BIT 5
1
0
0
1
0
0
0
0
DM_
PULLUP
BIT 4
0
0
1
1
0
1
0
0
DP_
PULLUP
BIT 3
1
1
0
0
1
1
0
0
BIT 2
0
0
0
0
0
0
0
0
BDISC_
ACONN
BIT 1
1
1
1
1
0
1
1
0
IRQ_MODE
BIT 0
0
1
1
1
0
0
0
1
Control
Register 2
11h
V BUS_
DISCHG
V BUS_DRV
V BUS_CHG2 V BUS_CHG1
SDWN
Reserved
Status
Register
Interrupt Mask
Interrupt Edge
Interrupt
Latch
Reserved
12h
13h
14h
15h
16h
17h -Ffh
A_HNP_RQ
B_HNP
ID_
FLOAT_RQ
A_HNP
A_HNP_EN
ID_
GND_RQ
ID_FLOAT
ID_
FLOAT_EN
SESSION_
END_RQ
ID_GND
ID_
GND_EN
SESSION_
VALID_RN
SESSION_
END
SESSION_
END_EN
V BUS_
VALID_RN
SESSION_
VALID
SESSION_
VALID_EN
SESSION_
VALID_ED
SESSION_
VALID_RP
V BUS_VALID
V BUS_
VALID_EN
V BUS_
VALID_ED
V BUS_
VALID_RP
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