参数资料
型号: MAX3507EGI+T
厂商: Maxim Integrated Products
文件页数: 10/12页
文件大小: 0K
描述: IC AMP CATV UPSTREAM 28QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 可变增益放大器
应用: CATV
安装类型: 表面贴装
封装/外壳: 28-VFQFN 裸露焊盘
供应商设备封装: 28-QFN/MLP 裸露焊盘(5x5)
包装: 带卷 (TR)
Detailed Description
Internal Filter
The internal filter consists of an input transconductance
amplifier, a balanced fifth-order elliptic active lowpass
filter, and an offset-correction feedback network. The
signal at the output of the filter is level-shifted into the
programmable-gain amplifier.
The transconductance amplifier provides a high input
impedance to the user, and current drives the filter to
minimize insertion loss. The filter is a Gm-C topology to
provide sufficient bandwidth and linearity. The cutoff
frequency of the filter is fixed at 75MHz, while the spec-
ified stopband attenuation is met at 120MHz.
The internal offset-correction feedback network
removes any DC offset at the output of the filter. An off-
set voltage at this node would generate a transient dur-
ing a TX-enable or -disable transition, which would not
be acceptable. The offset-correction loop effectively
AC-couples the filter output to the programmable-gain
amplifier input. The network generates a highpass cor-
ner frequency at:
f-3dB(kHz) = 12.5/C(F)
Specified performance is achieved when the input is
driven differentially. The MAX3507 may be driven sin-
gle-ended. To drive the device in this manner, one of
the input pins must be capacitively coupled to ground.
Use a capacitor whose value is large enough to allow
for a low-impedance path to ground at the lowest fre-
quency of operation. For operation down to 5MHz, a
0.001F capacitor is suggested.
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA) consists of the
variable-gain amplifier (VGA) and the digital-to-analog
converter (DAC), which provide better than 55dB of
output-level control in 0.5dB steps. The PGA is imple-
mented as a programmable Gilbert-cell attenuator. It
uses a differential architecture to achieve maximum lin-
earity. The gain of the PGA is determined by a 7-bit
MAX3507
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
_______________________________________________________________________________________
7
Pin Description
PIN
NAME
DESCRIPTION
1
BIASF
Filter Bias. Connect to GND.
2
DC+
Filter Offset Correction. Connect 0.1F capacitor between this pin and DC-.
3
DC-
Filter Offset Correction. Connect 0.1F capacitor between this pin and DC+.
4, 8, 12, 23, 26
GND
Ground
5, 22, 25
VCC
+5V Supply. Bypass this pin to GND with a 0.1F capacitor as close to the part as possible.
6
IN+
Positive Input. Along with IN-, this port forms a high-impedance differential input to the filter.
7
IN-
Negative Input. When not used, this port must be AC-coupled to ground. See IN+.
9
CS
Serial Interface Enable (Chip Select). TTL-compatible input. See Serial Interface section.
10
SDA
Serial Interface Data (Serial Data). TTL-compatible input. See Serial Interface section.
11
SCLK
Serial Interface Clock (Serial Clock). TTL-compatible input. See Serial Interface section.
13, 15, 17, 20, 24
N.C.
No Connection. Not internally connected.
14
SHDN
Shutdown. When SHDN is set low, all functions (including the serial interface) are disabled.
16
CEXT
RF Output Bypass. Bypass to ground with a 0.1F capacitor.
18
OUT-
Negative Output. Along with OUT+, this port forms a 300
impedance output. This port is matched
to a 75
load using a 2:1 (voltage ratio) transformer.
19
OUT+
Positive Output. See OUT-.
21
TXEN
Signal Path Enable. Setting this pin low turns off the PGA and power amplifier, leaving the filter
and serial interface enabled to save the last gain setting.
27
EQ+
Positive Equalizer. Connect an RC network if equalization of the filter passband is desired; leave
open otherwise. See Typical Operating Characteristics.
28
EQ-
Negative Equalizer. Connect an RC network if equalization of the filter passband is desired; leave
open otherwise. See Typical Operating Characteristics.
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