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参数资料
| 型号： | MAX3637ETM+ |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, QCC48 |
| 封装： | 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-48 |
| 文件页数： | 3/23页 |
| 文件大小： | 2745K |
| 代理商： | MAX3637ETM+ |
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3637
11
output interface. A PLL bypass mode is also available for
system testing or clock distribution.
Crystal Oscillator
The on-chip crystal oscillator provides the low-frequency
reference clock for the PLL. This oscillator requires an
external crystal connected between XIN and XOUT.
See the Crystal Selection and Layout section for more
information. The XIN and XOUT pins can be left open if
not used.
LVCMOS Clock Input
An LVCMOS-compatible clock source can be connected
to CIN to serve as the PLL reference clock. The input is
internally biased to allow AC- or DC-coupling (see the
Applications Information section). It is designed to oper-
ate from 15MHz to 160MHz. No signal should be applied
to CIN if not used.
Differential Clock Input
A differential clock source can be connected to DIN
to serve as the PLL reference clock. This input oper-
ates from 15MHz to 350MHz and contains an internal
100ω differential termination. This input can accept
DC-coupled LVPECL signals, and is internally biased to
accept AC-coupled LVDS, CML, and LVPECL signals
(see the Applications Information section). No signal
should be applied to DIN if not used.
Phase-Locked Loop (PLL)
The PLL takes the signal from the crystal oscillator,
LVCMOS clock input, or differential clock input and syn-
thesizes a low-jitter, high-frequency clock. The PLL con-
tains a phase-frequency detector (PFD), a charge pump
(CP), and a low phase noise VCO with a wide 3.60GHz to
3.83GHz frequency range. The high-frequency VCO out-
put is divided by prescale divider P, then is connected to
the PFD input through a feedback divider. The PFD com-
pares the reference frequency to the divided-down VCO
output and generates a control signal that keeps the
VCO locked to the reference clock. The high-frequency
VCO/P output clock is sent to the output dividers. To
minimize noise-induced jitter, the VCO supply (VCCA) is
isolated from the core logic and output buffer supplies.
Dividers and Muxes
The dividers and muxes are set with three-level control
inputs. Leakage in the NC case must be less than 1A.
Divider settings and routing information are given in
Tables 1 to 7. See Table 11 for example divider configu-
rations used in various applications.
Table 1. PLL Input
Table 2. PLL Bypass
IN_SEL
INPUT
0
Crystal Input. XO circuit is disabled when not selected.
1
Differential Input. No signal should be applied to DIN if not selected.
NC
LVCMOS Input. No signal should be applied to CIN if not selected.
PLL_BP
PLL OPERATION
0
PLL Enabled for Normal Operation. All outputs from the A, B, and C banks are derived from the VCO.
1
PLL Bypassed. Selected input passes directly to the outputs. The VCO is disabled to minimize power consump-
tion and intermodulation spurs. Used for system testing or clock distribution.
NC
The outputs from A-bank and B-bank are derived from the VCO, but the C-bank outputs are directly driven from
the input signal for purposes of daisy chaining.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3637ETM+ | 功能描述:时钟发生器及支持产品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX3637ETM+T | 功能描述:时钟发生器及支持产品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX3637EVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3637 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3637 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3637 |
| MAX3638ETM+ | 功能描述:时钟发生器及支持产品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX3638ETM+T | 功能描述:时钟发生器及支持产品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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