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| 型号： | MAX3680EAI |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC DESERIALZR 622MBPS TTL 28SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 46 |
| 功能： | 解串器 |
| 数据速率： | 622Mbps |
| 输入类型： | PECL |
| 输出类型： | TTL |
| 输入数： | 1 |
| 输出数： | 8 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
MAX3680/MAX3680A
Detailed Description
The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
4
_______________________________________________________________________________________
Pin Description
8-BIT
SHIFT
REGISTER
8-BIT
PARALLEL
OUTPUT
REGISTER
3-BIT
COUNTER
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK
TTL
PECL
SYNC
MAX3680/
MAX3680A
SD+
SD-
SCLK+
SCLK-
Figure 1. Functional Diagram
PIN
MAX3680
MAX3680A
NAME
FUNCTION
1, 2, 5, 8,
14, 18, 25
1, 2, 5, 8,
14, 18, 25
VCC
+3.3V Supply Voltage
3
SD+
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
SCLK+
Noninverting PECL Serial Clock Input
7
SCLK-
Inverting PECL Serial Clock Input
9, 11, 12,
16, 20, 23,
27
11, 12, 16,
20, 23, 27
GND
Ground
10
—
SYNC
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
—
9, 10
N.C.
No Connection
13
PCLK
TTL Parallel Clock Output
15, 17, 19,
21, 22, 24,
26, 28
15, 17, 19,
21, 22, 24,
26, 28
PD0–PD7
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3680EAI+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3680EAI+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3680EAI-T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3680EVKIT | 功能描述:界面开发工具 Evaluation Kit for the MAX3680 RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| MAX3681EAG | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Deserializ RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
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