参数资料
型号: MAX3681EAG+T
厂商: Maxim Integrated Products
文件页数: 4/8页
文件大小: 0K
描述: IC 1:4 DESERIALIZR W/LVDS 24SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
功能: 解串器
数据速率: 622Mbps
输入类型: LVDS
输出类型: LVDS
输入数: 1
输出数: 4
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 带卷 (TR)
MAX3681
_______________Detailed Description
The MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
NAME
FUNCTION
1, 2, 5, 8, 12
VCC
+3.3V Supply Voltage
3
SD+
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
PIN
4
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
SCLK+
Noninverting PECL Serial Clock Input
11
SYNC-
Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
10
SYNC+
Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
9, 15, 22
GND
Ground
7
SCLK-
Inverting PECL Serial Clock Input
17, 19, 21, 24
PD0+ to PD3+
Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
16, 18, 20, 23
PD0- to PD3-
Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
14
PCLK+
Noninverting LVDS Parallel Clock Output
13
PCLK-
Inverting LVDS Parallel Clock Output
4-BIT
SHIFT
REGISTER
4-BIT
PARALLEL
OUTPUT
REGISTER
2-BIT
COUNTER
LVDS
PECL
LVDS
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
SD+
SD-
SCLK+
SCLK-
SYNC+
SYNC-
100
Ω
MAX3681
Figure 1. Functional Diagram
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