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| 型号： | MAX3690ECJ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC SERIALIZR 622MBPS TTL 32-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 250 |
| 功能： | 串行器 |
| 数据速率： | 622Mbps |
| 输入类型： | TTL |
| 输出类型： | PECL |
| 输入数： | 8 |
| 输出数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
NAME
FUNCTION
1–8
PD0–PD7
TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
9, 10, 17,
18, 19, 24,
25, 26,
31, 32
GND
Ground
PIN
11
PCLKO
TTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management
circuit.
12, 13, 16,
21, 28, 29
VCC
+3.3V Supply Voltage
20
CKSET
Reference Clock Rate Programming Pin.
CKSET = open: Reference clock rate = 77.76MHz
CKSET = 20k
to GND: Reference clock rate = 51.84MHz
CKSET = GND: Reference clock rate = 38.88MHz
15
SD+
Noninverting PECL Serial-Data Output
14
SD-
Inverting PECL Serial-Data Output
30
PCLKI
TTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The
active edge is the positive transitioning edge.
27
RCLK
TTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to
the RCLK input. The active edge is the positive transitioning edge.
23
FIL+
Filter Capacitor Input. Connect a 1F capacitor between FIL- and VCC.
_______________Detailed Description
The MAX3690 serializer comprises an 8-bit parallel
input register, an 8-bit shift register, control and timing
logic, a PECL output buffer, TTL input/output buffers,
and a frequency-synthesizing PLL (consisting of a
phase/frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and programmable prescaler).
This device converts 8-bit-wide, 77Mbps parallel data
to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622MHz reference
used to clock the output shift register. This clock is
generated by locking onto the external crystal refer-
ence clock signal (RCLK) operating at either
77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-
allel data is clocked into the MAX3690 on the rising
transition of the parallel-clock-input signal (PCLKI). The
control and timing logic ensure proper operation if the
parallel-input register is latched within a window of time
that is defined with respect to the parallel-clock-output
signal (PCLKO). PCLKO is the synthesized 622MHz
internal serial-clock signal divided by eight. Parallel-
clock output to parallel-clock-input delay (skew) must
be observed. Figure 2 shows the timing diagram.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50
DC termination to (VCC - 2V). See the Alternative PECL-
Output Termination section.
22
FIL-
Filter Capacitor Input. Connect a 1F capacitor between FIL- and VCC.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3690ECJ+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Serializer RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3690ECJ+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Serializer RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3690ECJT | 制造商:MAXIM 功能描述:New |
| MAX3690ECJ-T | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3690EVKIT | 功能描述:界面开发工具 Evaluation Kit for the MAX3690 RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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