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参数资料
| 型号： | MAX3693ECJ+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/8页 |
| 文件大小： | 0K |
| 描述： | IC 4:1 SERIALIZER 622MBPS 32TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 250 |
| 功能： | 串行器 |
| 数据速率： | 622Mbps |
| 输入类型： | LVDS |
| 输出类型： | PECL |
| 输入数： | 4 |
| 输出数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 托盘 |
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
4
_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC = +3.3V, differential LVDS loads = 100 ±1%, PECL loads = 50 ±1% to (VCC - 2V), TA = +25°C, unless otherwise noted.)
1.1V
0.536V
200ps/div
SERIAL-DATA OUTPUT EYE DIAGRAM
57mV/
div
MAX3693-05
1.0042V
0.904V
10ps/div
SERIAL-DATA OUTPUT JITTER
10mV/
div
MAX3693-06
Mean 25.22ns
RMS 4.073ps
PkPk
32.6ps
±1σ 70.373%
±2σ 95.357%
±3σ 99.759%
fRCLK = 155.52MHz
Pin Description
NAME
FUNCTION
1, 3, 5, 7
PD0+ to PD3+
Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
2, 4, 6, 8
PD0- to PD3-
Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
PIN
9, 17, 18, 19,
24, 25, 32
GND
Ground
10
PCLKO-
Inverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead man-
agement circuit.
15
SD+
Noninverting PECL Serial-Data Output
14
SD-
Inverting PECL Serial-Data Output
12, 13, 16,
21, 28, 29
VCC
+3.3V Supply Voltage
11
PCLKO+
Noninverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead
management circuit.
23
FIL+
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
22
FIL-
Filter Capacitor Input. See Typical Operating Circuit for external-component connections.
26
RCLK+
Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to
the RCLK inputs.
30
PCLKI+
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
27
RCLK-
Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the
RCLK inputs.
31
PCLKI-
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
20
CKSET
Reference Clock Rate Programming Pin.
CKSET = VCC: Reference Clock Rate = 155.52MHz
CKSET = Open: Reference Clock Rate = 77.76MHz
CKSET = 20k to GND: Reference Clock Rate = 51.84MHz
CKSET = GND Reference Clock Rate = 38.88MHz
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX3693ECJ+ | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Serializer RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3693ECJ+T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Serializer RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3693ECJ-T | 功能描述:串行器/解串器 - Serdes 3.3V 622Mbps SDH/ SONET 1:8 Serializer RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX3697AETJ+ | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR 32TQFN |
| MAX3697AETJ+T | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR 32TQFN |
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