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参数资料
| 型号： | MAX3815ACCM+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/11页 |
| 文件大小： | 0K |
| 描述： | IC DGTL VIDEO EQUALIZER 48TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 250 |
| 类型： | 视频均衡器 |
| 应用： | HDMI，DVI，接收器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
8 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Applications Information
Typical shielded twisted pair (STP), unshielded twisted
pair (UTP), and twin-ax cables exhibit skin-effect losses,
which attenuate the high-frequency spectrum of a TMDS
signal, eventually causing data errors or even closing
the signal eye altogether given a long enough cable. The
MAX3815A recovers the data and opens the signal eye
through compensating equalization.
The basic TMDS interface is composed of four differential
serial links: three links carry serial data up to 2.25Gbps
each, and the fourth is a one-tenth-rate (0.1x) clock that
operates up to 225MHz. TMDS, as with analog nVGA
links, must handle a variety of resolutions and screen
update rates. The actual range of digital serial rates is
roughly 250Mbps to 2.25Gbps. For applications requir-
ing ultra-high resolutions (e.g., QXGA), a “dual-link” DVI
interface is used and is composed of six data links plus
the clock, requiring two MAX3815A ICs with the clock
going to both ICs. See Figure 2.
The MAX3815A can be used to extend any TMDS inter-
face as used under the following trademarked names:
DVI (digital visual interface), DFP (digital flat-panel),
PanelLink, ADC (Apple display connector), and HDMI
(high-definition multimedia interface).
Loss-of-Clock Signal (CLKLOS) Output
A loss-of-clock signal is indicated by the CLKLOS out-
put. A low level on CLKLOS indicates that the signal
power on the RXC_IN pins has dropped below a thresh-
old. When there is sufficient input voltage to the channel
(typically greater than 100mVP-P differential), CLKLOS is
high. The CLKLOS output is suitable for indicating prob-
lems with the transmission link caused by, for example,
a broken cable, a defective driver, or a lost connection
to the equalizer. Note that the loss-of-clock circuitry is
sensitive to a DC or AC voltage between the RXC_IN
pins. A DC or AC voltage greater than Q30mV (typical) is
sensed as an active clock signal.
Figure 2. Connection Scheme for MAX3815A in Dual Link
Application
DFP is a trademark of Video Electronics Standards Association (VESA).
ADC is a trademark of Apple Computer, Inc.
Figure 4. Back Termination Circuit
Figure 3. Simplified CLKLOS Output Circuit Schematic
D0
D1
D2
D3
D4
D5
D0
D1
D2
D3
D4
D5
CLK
MAX3815A
RX_OUT-
267
50
+3.3V
50
RX_OUT+
12.5mA
HDM/DVI
RECEIVER
VCC
CLKLOS
TO CHIP POWER-
CONTROL CIRCUITRY
4.7k
MAX3815A
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相关代理商/技术参数 |
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|---|---|
| MAX3815ACCM+ | 功能描述:IC DGTL VIDEO EQUALIZER 48TQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 标准包装:250 系列:- 类型:电平移位器 应用:LCD 电视机/监控器 安装类型:表面贴装 封装/外壳:28-WFQFN 裸露焊盘 供应商设备封装:28-WQFN（4x4）裸露焊盘 包装:带卷 (TR) 其它名称:296-32523-2TPS65198RUYT-ND |
| MAX3815ACCM+T | 功能描述:IC DGTL VIDEO EQUALIZER 48TQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| MAX3815AHDMIEVKIT+ | 功能描述:视频 IC 开发工具 Maxim Evaluation Kit RoHS:否 制造商:Texas Instruments 产品:Evaluation Boards 类型:YPbPr to RGBHV Converters 工具用于评估:LMH1251 工作电源电压:5 V |
| MAX3815CCM+ | 制造商:Maxim Integrated Products 功能描述:DGTL VID EQUALIZER 48TQFP EP - Rail/Tube |
| MAX3815CCM+D | 功能描述:均衡器 TMDS Digi Video EQ for HDMI/DVI Cables RoHS:否 制造商:Texas Instruments |
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