参数资料
型号: MAX3815ACCM+T
厂商: Maxim Integrated Products
文件页数: 8/11页
文件大小: 0K
描述: IC DGTL VIDEO EQUALIZER 48TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
类型: 视频均衡器
应用: HDMI,DVI,接收器
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 带卷 (TR)
6 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 8, 9,
12, 13, 16, 38
VCC
Supply Voltage. All pins must be connected to VCC.
2
RX0_IN-
Negative Data Input, CML
3
RX0_IN+
Positive Data Input, CML
6
RX1_IN-
Negative Data Input, CML
7
RX1_IN+
Positive Data Input, CML
10
RX2_IN-
Negative Data Input, CML
11
RX2_IN+
Positive Data Input, CML
14
RXC_IN+
Positive Clock Input, CML
15
RXC_IN-
Negative Clock Input, CML
17
EQCONTROL
Equalizer Control. This pin allows the user to control the equalization level of the MAX3815A.
Connect the pin to GND for automatic operation. Set the voltage to VCC - 1V for minimum
equalization, or set the voltage between VCC - 1V and VCC for manual equalization. See the
Applications Information section for more information.
18
CLKLOS
Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input
TMDS clock from the cable. Connect pin to VCC through a 4.7kω resistor.
19
N.C.
Not Connected. This pin is not internally connected.
20, 23, 24, 25,
28, 29, 32, 33,
36, 37
GND
Ground
21
RXC_OUT-
Negative Clock Output, CML
22
RXC_OUT+
Positive Clock Output, CML
26
RX2_OUT+
Positive Data Output, CML
27
RX2_OUT-
Negative Data Output, CML
30
RX1_OUT+
Positive Data Output, CML
31
RX1_OUT-
Negative Data Output, CML
34
RX0_OUT+
Positive Data Output, CML
35
RX0_OUT-
Negative Data Output, CML
39
OUTLEVEL
Output-Level Control Input
HIGH: Standard swing (1000mVP-P differential)
OPEN: Standard swing (900mVP-P differential) with external 267ω back termination resistor
(see Figure 4)
LOW: One-half standard swing (500mVP-P differential)
40
OUTON
Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and
sets a differential logic zero when forced high.
41, 43, 44
VCC_T
Reserved. Must be connected to VCC for normal operation.
42
GND_T
Reserved. Must be connected to GND for normal operation.
45–48
RES
Reserved. Must be left open for normal operation.
EP
Exposed Pad. The exposed pad must be soldered to the circuit-board ground for proper
thermal and electrical operation.
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