![](http://datasheet.mmic.net.cn/Maxim-Integrated-Products/MAX3861EGG_datasheet_105624/MAX3861EGG_6.png)
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
6
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1TH
Input Signal Detect Threshold Programming Pin. Attach a resistor between this pin and ground to
program the input signal detect assert threshold. Leaving this pin open sets the signal detect
threshold to its absolute minimum value (<2mVP-P). See the Design Procedure section.
2, 5, 14, 17
VCC
Supply Voltage Connection. Connect all VCC pins to the board VCC plane.
3
IN+
Positive CML Signal Input with On-Chip Termination Resistor
4
IN-
Negative CML Signal Input with On-Chip Termination Resistor
6EN
Signal Detect Enable. Set high (
≥2.0V) or leave open to enable the input signal detection (RSSI and
SD) circuitry. Set low (
≤0.4V) to power down the input signal detection circuitry.
7VREF
Reference Voltage Output (2.0V). Connect this pin to the SC pin for maximum output signal swing.
8SC
Output Amplitude External Control. Ground SC for minimum output amplitude. Apply 2.0V to SC or
connect SC directly to VREF for maximum output amplitude.
9, 12, 22
GND
Ground. Connect all GND pins to the board ground plane.
10
CG+
Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.
11
CG-
Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.
13
OSM
Output Signal Monitor. This DC signal is linearly proportional to the output signal amplitude.
15
OUT-
Negative CML Data Output with On-Chip Back-Termination Resistor
16
OUT+
Positive CML Data Output with On-Chip Back-Termination Resistor
18
SD
Input Signal Detect. Asserts logic low when the input signal level drops below the programmed
threshold.
19
RSSI
Received Signal Strength Indicator. Outputs a DC signal linearly proportional to the input signal
amplitude.
20
CD-
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.
21
CD+
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.
23
CZ-
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.
24
CZ+
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.
EP
Exposed Pad
Maxim recommends connecting the exposed pad to board ground.