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| 型号： | MAX3872ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC DATA RECOVERY W/AMP 32-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.67GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
Input Terminations
The SDI
± and SLBI± inputs of the MAX3872 are current-
mode logic (CML) compatible. The inputs all provide
internal 50
Ω termination to reduce the required number
of external components. AC-coupling is recommended.
See Figure 8 for the input structure. For additional infor-
mation on logic interfacing, refer to Maxim Application
Note HFAN 1.0:
Introduction to LVDS, PECL, and CML.
Output Terminations
The MAX3872 uses CML for its high-speed digital out-
puts (SDO
± and SCLKO±). The configuration of the out-
put circuit includes internal 50
Ω back terminations to
VCC. See Figure 9 for the output structure. CML outputs
can be terminated by 50
Ω to VCC, or by 100Ω differen-
tial impedance. For additional information on logic inter-
facing, refer to Maxim Application Note HFAN 1.0:
Introduction to LVDS, PECL, and CML.
Applications Information
Clock Holdover Capability
Clock holdover is required in some applications in
which a valid clock must be provided to the upstream
device in the absence of data transitions. To provide
this function, an external reference clock signal must
be applied to the SLBI
± inputs and the proper control
signals set (see the
Modes of Operation section). To
enter holdover mode automatically when there are no
transitions applied to the SDI
± inputs, LOL or the sys-
tem LOS can be directly connected to LREF.
System Loopback
The MAX3872 is designed to allow system loopback
testing. When the device is set for system loopback
mode, the serial output data of a transmitter may be
directly connected to the SLBI inputs to run system
diagnostics. See Table 1 for selecting system loopback
operation mode. While in system loopback mode, LREF
should not be connected to LOL.
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
______________________________________________________________________________________
11
50
Ω
50
Ω
VCC
SDI-
SDI+
MAX3872
Figure 8. CML Input Model
MAX3872
SDO-
SDO+
VCC
50
Ω
50
Ω
Figure 9. CML Output Model
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| MAX3872EVKIT | 功能描述:计时器和支持产品 Evaluation Kit for the MAX3872 MAX3874 RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| MAX3873AEGP | 功能描述:计时器和支持产品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| MAX3873AEGP+ | 制造商:Maxim Integrated Products 功能描述:CLOCK RECOVERY 20QFN - Bulk |
| MAX3873AEGP-T | 功能描述:计时器和支持产品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| MAX3873AETP+ | 功能描述:计时器和支持产品 2.5/2.7Gbps Clk-Reco & Data-Retiming IC RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
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