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参数资料
| 型号： | MAX4003EUA+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC LOG AMP RF DETECT 45DB 8-MSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 100MHz ~ 2.5GHz |
| RF 型： | 手机，TDMA，CDMA，GPRS，GSM |
| 输入范围： | -45dBm ~ 0dBm |
| 电源电压： | 2.7 V ~ 5 V |
| 电流 - 电源： | 5.9mA |
| 包装： | 带卷 (TR) |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
100MHz to 2500MHz, 45dB RF Detector
in a UCSP
Pin Description
PIN
μMAX/
Thin QFN
1
2
3, 5
4
6
7
8
UCSP
A1
A2
A3, C3
B3
—
C2
B1, C1
NAME
RFIN
SHDN
GND
CLPF
N.C.
OUT
V CC
DESCRIPTION
RF Input. Requires off-chip 50 ? impedance match.
Shutdown Input. A logic LOW on SHDN shuts down the entire IC.
Ground. Connect to PC board ground plane.
Lowpass Filter Connection. Connect external capacitor between CLPF and GND to set the
control-loop bandwidth.
No Connection. Leave this pin unconnected or connect to GND.
Detector Output. Connect this buffer output to baseband ADC.
Supply Voltage. Bypass with capacitor as close to the pin as possible. The bypass capacitor
must not share its ground vias with any other branches.
Detailed Description
The MAX4003 logarithmic amplifier comprises four
main amplifier/limiter stages, each with a small-signal
gain of 10dB. The output stage of each amplifier/limiter
stage is applied to a full-wave rectifier (detector). A
detector stage also precedes the first stage. In total,
five detectors, each separated by 10dB, comprise the
logarithmic amplifier strip (see Functional Diagram ).
A portion of the PA output power is coupled into RFIN
of the logarithmic amplifier detector through a direction-
al coupler, and is applied to the logarithmic amplifier
strip. Each detector stage generates a rectified current,
and these currents are summed to form a logarithmic
function. The detected output is applied to a high-gain
transconductance (g m ) stage, which is buffered and
then applied to OUT. OUT is applied to an ADC typical-
ly found in the baseband IC which, in turn, controls the
PA biasing with its DAC output (Figure 1).
In a control loop, the detector output voltage range is
approximately 0.36V for the minimum input signal,
-45dBm, to 1.45V at the maximum input range, 0dBm.
The logarithmic intercept of the detector output with
respect to the RF input can be obtained by drawing a
best fit line of the Output Voltage vs. RF Input Power
graph. The logarithmic slope is defined as the change
in the detector output vs. the change in RF input. The
MAX4003 slope at low frequencies is approximately
25.5mV/dB. Variation in temperature and supply volt-
age does not alter the slope significantly, as shown in
the Typical Operating Characteristics .
Applications Information
Filter Capacitor and Transient Response
In general, the choice of filter only partially determines
the time-domain response of a PA detector loop.
However, some simple conventions may be applied to
XX
PA
TRANSMITTER
discuss transient response. A large filter capacitor,
C CLPF , dominates time-domain response, but the loop
bandwidth remains a factor of the PA gain-control range
50 ?
DAC
(see Typical Operating Characteristics) . The bandwidth
50 ?
RFIN
SHDN
MAX4003
V CC
OUT
V CC
0.01 μ F
BASEBAND
IC
is maximized at power outputs near the center of the
PA’s range and minimized at the low and high power lev-
els, when the slope of the gain control curve is lowest.
A smaller valued C CLPF results in an increased-loop
GND
N.C.
ADC
bandwidth inversely proportional to the capacitor value.
Inherent phase lag in the PA’s control path, usually
caused by parasitics at the OUT pin, ultimately results
C CLPF
CLPF
GND
in the addition of complex poles in the AC loop equa-
tion. To avoid this secondary effect, experimentally
determine the lowest usable C CLPF for the power ampli-
Figure 1. MAX4003 Typical Application Circuit
8
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