参数资料
型号: MAX4322ESA+T
厂商: Maxim Integrated Products
文件页数: 3/17页
文件大小: 0K
描述: IC OP AMP R-R I/O LP 8-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
放大器类型: 通用
电路数: 1
输出类型: 满摆幅
转换速率: 2 V/µs
增益带宽积: 5MHz
电流 - 输入偏压: 50nA
电压 - 输入偏移: 700µV
电流 - 电源: 725µA
电流 - 输出 / 通道: 50mA
电压 - 电源,单路/双路(±): 2.4 V ~ 6.5 V,±1.2 V ~ 3.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
Figures 9 and 10 show the output voltage and supply
current on power-up of the test circuit in Figure 8.
The MAX4323 and MAX4327 have a shutdown option.
When shutdown (SHDN) is pulled low, the supply cur-
rent drops to 25A per amplifier and the amplifiers are
disabled with the outputs in a high-impedance state.
Pulling SHDN high or leaving it floating (1A internal
pullup) enables the amplifier. In the dual-amplifier
MAX4327, the shutdown functions operate indepen-
dently. Figures 11 and 12 show the output voltage and
supply current responses of the MAX4323 to a shut-
down pulse.
Power Supplies and Layout
The MAX4322/MAX4323/MAX4326/MAX4327/MAX4329
operate from a single 2.4V to 6.5V power supply, or
from dual supplies of ±1.2V to ±3.25V. For single-supply
operation, bypass the power supply with a 0.1F
ceramic capacitor in parallel with at least 1F. For dual
supplies, bypass each supply to ground.
Good layout improves performance by decreasing the
amount of stray capacitance at the op amp’s inputs and
outputs. To decrease stray capacitance, minimize trace
lengths and resistor leads by placing external compo-
nents close to the op amp.
UCSP Information
Layout Issues
Design the layout for the device to be as compact as
possible to minimize parasitics. The UCSP uses a
bump pitch of 0.5mm (19.7mil) and a bump diameter of
0.33mm (~12mil). Therefore, lay out the solder-pad
spacing on 0.5mm (19.7mil) centers, using a pad size
of 0.25mm (~10mil) and a solder mask opening of
0.33mm (13mil). Round or square pads are permissi-
ble. Connect multiple vias from the ground plane as
close to the ground connections as possible.
Install capacitors as close as possible to the device
supply voltage input. Place the ground end of these
capacitors near the ground plane to provide a low-
impedance return path for the signal current.
Prototype Chip Installation
Alignment keys on the PC board, around the area
where the chip is located, are helpful in the prototype
assembly process. It is better to align the chip on the
board before any other components are placed, and
then place the board on a hot plate or hot surface until
the solder starts melting. Remove the board from the
hot plate without disturbing the position of the chip and
let it cool down to room temperature before processing
the board further.
MAX4322/MAX4323/MAX4326/MAX4327/MAX4329
Single/Dual/Quad, Low-Cost, UCSP/SOT23,
Low-Power, Rail-to-Rail I/O Op Amps
______________________________________________________________________________________
11
AAA
ORIENTATION
PRODUCT ID CODE
LOT CODE
TOP VIEW
(BUMPS ON BOTTOM)
A2
A1
A3
MAX4323EBT (UCSP) Marking Information
RS
CL
MAX4322/MAX4323
MAX4326/MAX4327
MAX4329
Figure 7. Capacitive-Load-Driving Circuit
VOUT
0 TO 2.7V
STEP FOR
POWER-UP
TEST
SUPPLY-CURRENT
MONITORING POINT
VCC
10
2k
10k
2k
MAX4322/MAX4323
MAX4326/MAX4327
MAX4329
Figure 8. Power-Up Test Circuit
相关PDF资料
PDF描述
TSW-150-06-L-D CONN HEADER 100POS .100" DL GOLD
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MAX4322EUK 制造商:Maxim Integrated Products 功能描述:SINGLE/DUAL/QUAD LOW-COST UCSP/SOT23 LOW-POWER RAIL-TO-RAIL - Rail/Tube