参数资料
型号: MAX4358ECE+TD
厂商: Maxim Integrated Products
文件页数: 21/43页
文件大小: 0K
描述: IC VIDEO CROSSPOINT SWIT 144TQFP
产品变化通告: Product Discontinuation 28/Nov/2011
标准包装: 250
功能: 视频交叉点开关
电路: 1 x 32:16
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 5V,± 3 V ~ 5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-TQFP
供应商设备封装: 144-TQFP(20x20)
包装: 带卷 (TR)
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
28
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 35, 37,
39, 41, 43, 45, 127, 129, 131,
133, 135, 137, 139, 141, 143
IN0–IN31
Buffered Analog Inputs
2, 4, 6, 8, 10, 12, 14, 16, 18, 20,
22, 24, 26, 28, 30, 32, 34, 72, 73,
107, 108, 109, 126, 128, 130,
132, 134, 136, 138, 140, 142
AGND
Analog Ground
36, 74, 78, 82, 86, 90, 94, 98,
102, 106
VCC
Positive Analog Supply. Bypass each pin with a 0.1F capacitor to AGND.
Connect a single 10F capacitor from one VCC pin to AGND.
38, 40, 42, 44
A3–A0
Address Programming Inputs. Connect to DGND or VDD to select the address
for individual output address mode. See Table 4.
46
DGND
Digital Ground
47
AOUT
Address Recognition Output.
AOUT drives low after successful chip address
recognition.
48
MODE
Serial Interface Mode Select Input. Drive high for Complete Matrix Mode
(Mode 1), or drive low for Individual Output Address Mode (Mode 0).
49
DIN
Serial Data Input. Data is clocked-in on the falling edge of SCLK.
50
SCLK
Serial Clock Input
51
UPDATE
Update Input. Drive
UPDATE low to transfer data from Mode Registers to the
switch matrix.
52
RESET
Asynchronous Reset Input/Output. Drive
RESET low to initiate hardware reset.
All analog outputs are disabled. Additional power-on reset delay may be set
by connecting a small capacitor from
RESET to DGND.
53
CE
Clock Enable Input. Drive low to enable the serial data interface.
54
DOUT
Serial Data Output. In Complete Matrix Mode, data is clocked through the 112-
bit Matrix Control shift register. In Individual Output Address Mode, data at DIN
passes directly to DOUT.
55–70
OSDKEY0–
OSDKEY15
Digital Control Input. Control for the fast 2:1 OSD Insertion multiplexer routing
signal to output buffers. A logic high routes programmed IN_ analog input
signal to output buffer. A logic low routes the dedicated OSDFILL_ input to
corresponding output buffer.
71
VDD
Digital Logic Supply. Bypass VDD with a 0.1F capacitor to DGND.
75, 77, 79, 81, 83, 85, 87, 89, 91,
93, 95, 97, 99, 101, 103, 105
OUT0–
OUT15
Buffered Analog Outputs. Gain is individually programmable for AV = +1V/V or
AV = +2V/V via the serial interface. Outputs may be individually disabled (high
impedance). On power-up, or assertion of
RESET, all outputs are disabled.
76, 80, 84, 88, 92, 96, 100, 104,
144
VEE
Negative Analog Supply. Bypass each pin with a 0.1F capacitor to AGND.
Connect a single 10F capacitor from one VEE pin to AGND.
110, 111, 112, 113, 114, 115,
116, 117, 118, 119, 120, 121,
122, 123, 124, 125
OSDFILL15
–OSDFILL0
Dedicated OSD Analog Signal Buffered Inputs. For each output buffer
amplifier. OSDFILLi input signal is routed to output buffer amplifier OUTi when
the corresponding OSDKEYi is low.
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