参数资料
型号: MAX4544EUT-T
厂商: Maxim Integrated Products
文件页数: 14/16页
文件大小: 0K
描述: IC SWITCH SPDT SOT23-6
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
功能: 开关
电路: 1 x SPDT
导通状态电阻: 60 欧姆
电压电源: 单电源
电压 - 电源,单路/双路(±): 2.7 V ~ 12 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-6
包装: 剪切带 (CT)
其它名称: MAX4544EUT-TCT
Power-Supply Sequencing
and Overvoltage Protection
Do not exceed the absolute maximum ratings because
stresses beyond the listed ratings may cause perma-
nent damage to the devices.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals or logic inputs, especially if the analog
or logic signals are not current limited. If this sequenc-
ing is not possible, and if the analog or logic inputs are
not current limited to < 10mA, add a small-signal diode
(D1) as shown in Figure 1. If the analog signal can dip
below GND, add D2. Adding protection diodes
reduces the analog signal range to a diode drop (about
0.7V) below V+ (for D1), and to a diode drop above
ground (for D2). Leakage is unaffected by adding the
diodes. On-resistance increases by a small amount at
low supply voltages. Maximum supply voltage (V+)
must not exceed 13V.
Adding protection diodes causes the logic thresholds
to be shifted relative to the power-supply rails. This can
be significant when low supply voltages (+5V or less)
are used. With a +5V supply, TTL compatibility is not
guaranteed when protection diodes are added. Driving
IN1 and IN2 all the way to the supply rails (i.e., to a
diode drop higher than the V+ pin, or to a diode drop
lower than the GND pin) is always acceptable.
Protection diodes D1 and D2 also protect against
some overvoltage situations. With Figure 1’s circuit, if
the supply voltage is below the absolute maximum rat-
ing, and if a fault voltage up to the absolute maximum
rating is applied to an analog signal pin, no damage
will result.
MAX4541–MAX4544
Low-Voltage, Single-Supply
Dual SPST/SPDT Analog Switches
_______________________________________________________________________________________
7
tr < 20ns
tf < 20ns
50%
0
LOGIC
INPUT
RL
1k
Ω
COM
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VCOM
(
RL
)
RL + RON
SWITCH
INPUT
IN
+3V
tOFF
0
NO
or NC
SWITCH
OUTPUT
0.9 x V0UT
0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
CL
35pF
V+
VOUT
0V
MAX4541
MAX4542
MAX4543
MAX4544
Figure 2. Switching Time
Test Circuits/Timing Diagrams
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