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| 型号： | MAX4563EEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC AUD/VID SWITCH SPI SER 16QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 音频/视频切换 |
| 电路： | 2 x SPDT - NO，2 x SPST - NO |
| 导通状态电阻： | 60 欧姆 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
MAX4562/MAX4563
Serially Controlled, Clickless
Audio/Video Switches
______________________________________________________________________________________
11
Table 1. Command-Bit Mapping
C1
C0
COMMAND
DESCRIPTION
0
NO_OP
No Operation
0
1
NO_OP
No Operation
1
0
SWITCHSET
Sets specified switches open or closed.
1
MODESET
Sets specified switches to soft or hard mode.
Applications Information
Switch Control
The MAX4562/MAX4563 have a common command-
and control-bit structure; the only difference is the inter-
face type (2-wire or 3-wire).
The SWITCHSET command controls the open/closed
states of the various switches. MODESET controls
soft/hard-mode switch states. The NO_OP command is
useful for daisy-chaining multiple 3-wire parts.
Table 1 shows the command bits’ configuration and their
related commands. Table 2 shows the configuration of
the data bits and their related switches. After a SWITCH-
SET command is issued, a logic “1” in any data-bit loca-
tion closes the associated switch, while a logic “0”
opens it. After a MODESET command, a logic “1” in any
data-bit location sets the associated switch into soft
mode, while a logic “0” sets it into hard mode.
2-Wire Serial Interface
The MAX4562 uses a 2-wire I2C-compatible serial inter-
face, requiring only two I/O lines of a standard micro-
processor port for communication. These devices use
a SendByte protocol. The SendByte protocol consists
of one byte of address field followed by one byte of
command field.
The first byte of any 2-wire serial-interface transaction is
always the address byte. To address a given chip, the
A0 and A1 bits in the address byte (Table 3) must dupli-
cate the values present at the A0 and A1 pins of that
chip, and the rest of the address bits must be configured
as shown in Table 3. Connect the A0 and A1 pins to V+
or GND or drive them with CMOS logic levels.
The second byte is the command byte, which sets the
command being written to the device. The possible
commands are MODESET and SWITCHSET. Figures 3
and 4 and the
I/O Interface Characteristics detail the tim-
ing of the 2-wire serial-interface protocol. All bytes of the
transmission, whether address or command, are sent
MSB first.
The MAX4562/MAX4563 are receive-only devices and
must be controlled by a bus master device. A bus mas-
ter signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while
SCL is high. The slave devices monitor the serial bus
continuously, waiting for the start condition followed by
an address byte. When a device recognizes its address
byte, it acknowledges by pulling the SDA line low for one
clock period; it is then ready to accept the command
byte. The device also issues a similar acknowledgment
after the command byte. When the master has finished
communicating with the slave, it issues a stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
3-Wire Serial Interface
The MAX4563 uses a 3-wire SPI/QSPI/MICROWIRE-com-
patible serial interface. An active-low chip select (CS) pin
enables the device to receive data from the serial input
pin, DIN. Command and data information are clocked in
on the rising edge of the serial clock signal (SCLK) MSB
first. A total of eight bits is needed in each write cycle.
The command code is contained in the two MSBs of the
8-bit word. The remaining bits control the switches as
shown in Table 4. While shifting in the serial data, the
device remains in its original configuration. A rising edge
on CS latches the data into the MAX4563’s internal regis-
ter, initiating the device’s change of state. Table 4 shows
the details of the 3-wire interface structure.
Table 2. Control-Bit Mapping
CONTROL BIT
SWITCH
SWITCH TERMINAL
D1
D5
SW1A
2, 3
SW3
D4
SW1B
3, 4
9, 10
D3
SW2A
6, 7
D0 (LSB)
D2
SW2B
7, 8
SW4
11, 12
SendByte is a trademark of Philips Corp.
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