参数资料
型号: MAX4723EUA+T
厂商: Maxim Integrated Products
文件页数: 14/14页
文件大小: 0K
描述: IC SWITCH DUAL SPST 8UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 开关
电路: 2 x SPST - NC/NO
导通状态电阻: 4.5 欧姆
电压电源: 单电源
电压 - 电源,单路/双路(±): 1.8 V ~ 5.5 V
电流 - 电源: 1µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
Power-Supply Bypassing
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1F capacitor connect-
ed from V+ to GND is adequate for most applications.
Power-Supply Sequencing
and Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings may
cause permanent damage to the device.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
MAX4721/MAX4722/MAX4723
4.5
Dual SPST Analog Switches in UCSP
_______________________________________________________________________________________
9
Test Circuits/Timing Diagrams
50%
VIL
LOGIC
INPUT
RL
COM_
GND
IN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VCOM
VN_
VIH
tOFF
0V
NO_
OR NC_
0.9 x V0UT
0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
CL
V+
VOUT
MAX4721/
MAX4722/
MAX4723
(
RL
RL - RON )
Figure 1. Switching Time
LOGIC
INPUT
RL2
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
VOUT2
V+
CL2
MAX4723
RL1
CL1
VOUT1
VCOM1
VCOM2
50%
0.9 x V0UT1
VIH
VIL
0V
LOGIC
INPUT
SWITCH
OUTPUT 2
(VOUT2)
0V
0.9 x VOUT2
tD
SWITCH
OUTPUT 1
(VOUT1)
COM2
COM1
Figure 2. Break-Before-Make Interval
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