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参数资料
| 型号： | MAX4810CTN+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL PULSER DL 56TQFN-EP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 线性 - 单极，双极 |
| 电源电压： | 4.75 V ~ 12.6 V |
| 电流 - 电源： | 36mA |
| 电流 - 输出（最大）： | 1.3A |
| 输出类型： | 电压和电流 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 56-WFQFN 裸露焊盘 |
| 供应商设备封装： | 56-TQFN-EP（7x7） |
| 包装： | 带卷 (TR) |
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)
(V DD = +2.7V to +6V, V CC_ = +4.75V to +12.6V, V EE_ = -12.6V to -4.75V, V NN_ = -200V to 0, V PP_ = 0 to (V NN_ + 200V), V SS ≤ the lower of
V NN1 or V NN2 , T A = T J = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) (Note 3) (See Figures 8, 9, and 10.)
PARAMETER
Logic Input to Output-Fall
Propagation Delay Clamp
OUT_ Rise Time (GND to V PP_ )
OUT_ Rise Time (V NN_ to GND)
OUT_ Rise Time (V NN_ to V PP_ )
OUT_ Fall Time (GND to V NN_ )
OUT_ Fall Time (V PP_ to GND)
OUT_ Fall Time (V PP_ to V NN_ )
OUT Enable Time from EN
(Figure 5)
OUT Disable Time from EN
(Figure 5)
Clamp Enable Time from INC
(Figure 6)
Clamp Disable Time from INC
(Figure 6)
Short Enable Time from EN
(Figure 7)
Short Disable Time from EN
(Figure 7)
SYMBOL
t PHO
t R0P
t RN0
t RNP
t F0N
t FP0
t FPN
t EN
t DI
t EN-CL
t DI-CL
t EN_SH
t DI_SH
CONDITIONS
V CC_ = +12V, V PP_ = +5V, V NN_ = -5V, Figure 4
V PP_ = +100V, V NN_ = -100V, V CC_ = +12V ± 5%,
V EE_ = -V CC_ , Figure 4
V PP_ = +100V, V NN_ = -100V, V CC_ = +12V ± 5%,
V EE_ = -V CC_ , Figure 4
V PP_ = +100V, V NN_ = -100V, V CC_ = +12V ± 5%,
V EE_ = -V CC_ , Figure 4
V PP_ = +100V, V NN_ = -100V, V CC_ = +12V ± 5%,
V EE_ = -V CC_ , Figure 4
V PP_ = +100V, V NN_ = -100V, V CC_ = +12V ± 5%,
V EE_ = -V CC_ , Figure 4
V PP_ = +100V, V NN_ = -100V, V CC_ = +12V ± 5%,
V EE_ = -V CC_ , Figure 4
V CC_ = +12V ± 5%, V EE_ = -V CC_
V CC_ = +5V ± 5%, V EE_ = -V CC_
V CC_ = +12V ± 5%, V EE_ = -V CC_
V CC_ = +5V ± 5%, V EE_ = -V CC_
V CC_ = +12V ± 5%, V EE_ = -V CC_
V CC_ = +5V ± 5%, V EE_ = -V CC_
V CC_ = +12V ± 5%, V EE_ = -V CC_
V CC_ = +5V ± 5%, V EE_ = -V CC_
V PP_ = 12V, V NN_ = 0, V CC_ = +12V ± 5%,
V EE_ = -V CC_
V PP_ = 5V, V NN_ = 0, V CC_ = +5V ± 5%,
V EE_ = -V CC_
V PP_ = 12V, V NN_ = 0, V CC_ = +12V ± 5%,
V EE_ = -V CC_
V PP_ = 5V, V NN_ = 0, V CC_ = +5V ± 5%,
V EE_ = -V CC_
MIN
TYP
15
9
17
10.5
9
17
10.5
MAX
20
35
35
20
35
35
100
150
100
150
150
180
150
150
1000
1000
250
250
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INP_ to INN_ Overlap Tolerance
|3|
ns
Crosstalk
V PP_ = V CC_ = +5V, V NN_ = V EE_ = -5V,
f = 5MHz
69
dB
2nd Harmonic Distortion
RMS Output Jitter
2HD
t J
V PP_ = V NN_ = 100V, f OUT = 5MHz, V CC_ = 12V
V CC_ = 12V
-48
9
dB
ps
Note 3: Specifications are guaranteed for the stated global conditions, unless otherwise noted and are 100% production tested at
T A = +25°C and T A = +70°C. Specifications at T A = 0°C are guaranteed by design.
Note 4: 100% production tested at T A = +25°C. Specifications over temperature are guaranteed by design.
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