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参数资料
| 型号： | MAX4836ETT33C+T |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 固定正电压单路输出LDO稳压器 |
| 英文描述： | 500mA LDO Linear Regulators with Current-Limiting Switch |
| 中文描述： | 3.3 V FIXED POSITIVE LDO REGULATOR, 0.33 V DROPOUT, DSO6 |
| 封装： | 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-229WEEA, TDFN-6 |
| 文件页数： | 13/15页 |
| 文件大小： | 429K |
| 代理商： | MAX4836ETT33C+T |
Detailed Description
The MAX4836/MAX4837 are ultra-low quiescent current,
low-dropout linear regulators with an integrated current
limiter. These devices guarantee up to 500mA drive
capabilities and regulate the preset output voltage.
The MAX4836 has a flag output that asserts low when
the load current exceeds the current limit for more than
the blanking time (tBLANK). The MAX4837 has a reset
output that asserts low when the regulator output volt-
age is below the reset threshold voltage (VRESET).
VRESET is 87.5% of the nominal output voltage. Figure 1
shows the simplified functional diagram and Figure 2
shows the typical application circuits.
FLAG Output (MAX4836)
The open-drain FLAG output goes low and the LDO’s
pass transistor is latched off when the current in the
pass transistor is at its output current limit for more than
the blanking time (tBLANK). Cycling IN or SHDN (high to
low to high) brings the device out of its latched-off state
and back into normal operation.
RESET Output (MAX4837)
The RESET output asserts when one of the following
conditions occurs:
The input voltage (VIN) is below the input undervolt-
age lockout threshold (VUVLO).
The output voltage (VOUT) is below the reset thresh-
old (VRESET).
SHDN is pulled low.
The device is in thermal shutdown.
When VOUT > VIN.
RESET remains low for the reset timeout period (tRESET)
after reset conditions are terminated. There are four
RESET timeout periods available as shown in the
Electrical Characteristics table. RESET is available in a
push-pull configuration as shown in the Selector Guide.
Shutdown
Pull SHDN low to shut down the LDO and reduce the
quiescent current consumption of the device from 90A
to 0.1A. In shutdown mode, the pass transistor, con-
trol circuit, and reference circuit are turned off. Connect
SHDN to a supply voltage greater than VIH to turn on
the LDO.
MAX4836/MAX4837
500mA LDO Linear Regulators with
Current-Limiting Switch
_______________________________________________________________________________________
7
Pin Description
PIN
SOT23
TDFN
NAME
FUNCTION
11
IN
Regulator Power Input. Bypass IN to GND with a 0.1F ceramic capacitor. Install the bypass
capacitor as close to the device as possible.
2
GND
Ground
33
SHDN
Active-Low Shutdown Input. Drive SHDN low to shutdown the regulator. Drive SHDN high or
connect to IN for normal operation.
FLAG
(MAX4836)
Overcurrent Flag. Open-drain FLAG goes low when the device senses sustained current
exceeding the current-limit threshold for a duration longer than the blanking time. FLAG is high
when SHDN is low or the device is in thermal shutdown.
44
RESET
(MAX4837)
Active-Low Reset Output. Push-pull RESET goes low when the voltage at OUT is below the reset
threshold or when the voltage at OUT is greater than IN. RESET is low when SHDN is low or the
device is in thermal shutdown. After the reset condition terminates, RESET remains low for the
duration of the reset timeout period.
55
SS
Soft-Start Control. Connect a capacitor, CSS, from SS to GND to program the output rise time at
startup. No capacitor from SS to GND gives 1ms output rise time at startup. See the soft-start
response time plots in the Typical Operating Characteristics.
6
OUT
Regulator Output. Bypass OUT to GND with a 3.3F or larger ceramic capacitor. The capacitor’s
ESR should be less than 0.2
for stable operation.
—EP
EP
Exposed Pad. EP is internally connected to GND. Externally connect EP to GND to provide a low
thermal resistance path from the IC junction to the PC board.
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