参数资料
型号: MAX4867ELT+T
厂商: Maxim Integrated Products
文件页数: 5/11页
文件大小: 0K
描述: IC CTLR OVP REVERSE POL 6UDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
技术: 混合技术
电路数: 1
应用: 通用
封装/外壳: 6-WDFN
供应商设备封装: 6-uDFN(2x2)
包装: 带卷 (TR)
MAX4864L/MAX4865L/MAX4866L/MAX4867
Overvoltage Protection Controllers
with Reverse Polarity Protection
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +5V (MAX4864L/MAX4865L/MAX4866L), VIN = +4V (MAX4867), TA = -40°C to +85°C, CGATEN = 500pF, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EN Input Leakage Current
ILKG
EN = GND or +5.5V
1
A
TIMING
Startup Delay
tSTART
VIN > UVLO to VGATEN > 0.3V, Figure 1
20
50
80
ms
FLAG Blanking Time
tBLANK
VGATEN > 0.3V to VFLAG < 0.3V, Figure 1
20
50
80
ms
GATEN Turn-On Time
tGON
CGATEN = 500pF, VGATEN = 0.3V to +8V
(MAX4864L/MAX4865L/MAX4866L)
VGATEN = 0.3V to +7V (MAX4867), Figure 1
10
ms
GATEN Turn-Off Time
tGOFF
VIN rising at 3V/s from +5V to +8V
(MAX4864L/MAX4865L/MAX4866L),
or from +4V to +7V (MAX4867)
VGATEN = 0.3V, CGATEN = 500pF, Figure 2
720
s
FLAG Assertion Delay
tFLAG
VIN rising at 3V/s from 5V to 8V
(MAX4864L/MAX4865L/MAX4866L),
or from +4V to +7V (MAX4867), VFLAG = 0.3V,
Figure 2
3.5
s
Initial Overvoltage Fault Delay
tOVP
VIN rising at 3V/s from 0V to +9V, time from
VIN = 5V to IGATEN = 80% of IPD (GATEN pulldown
current), Figure 3
1.5
s
Disable Time
tDIS
V
EN = +2.4V, VGATEN = 0.3V, Figure 4
2
s
Note 1: All parts are 100% tested at +25°C. Electrical limits across the full temperature range are guaranteed by design and correlation.
VGATEN
VEN
+0.3V
+2.4V
tDIS
Figure 4. Disable Timing Diagram
VIN
VUVLO
tGON
tSTART
VGATEN
VFLAG
tBLANK
+0.3V
+8V (+7V)*
*MAX4867
+5V
+0.3V
Figure 1. Startup Timing Diagram
VIN
VOVLO
VGATEN
VFLAG
tFLAG
tGOFF
+0.3V
+5V
Figure 2. Shutdown Timing Diagram
VIN
VOVLO
tOVP
IGATEN
80%
0V
Figure 3. Power-Up Overvoltage Timing Diagram
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