参数资料
型号: MAX4927ETN+T
厂商: Maxim Integrated Products
文件页数: 12/13页
文件大小: 0K
描述: IC ETHERNET SWITCH QUAD 56TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 以太网开关
电路: 4 x 2:2
导通状态电阻: 5.5 欧姆
电压电源: 单电源
电压 - 电源,单路/双路(±): 3 V ~ 3.6 V
电流 - 电源: 280µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(5x11)
包装: 带卷 (TR)
MAX4927
1000 Base-T, ±15kV ESD Protection LAN Switch
8
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Human Body Model
Figure 5a shows the Human Body Model. Figure 5b
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through
1.5k
Ω resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. However, it does
not specifically refer to integrated circuits. The MAX4927
helps equipment design to meet IEC 61000-4-2 without
the need for additional ESD-protected components.
The major difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2 because series resistance is
lower in the IEC 61000-4-2 model. Hence, the ESD with-
stand voltage measured to IEC 61000-4-2 is generally
lower than that measured using the Human Body
Model. Figure 5c shows the IEC 61000-4-2 model, and
Figure 5d shows the current waveform for IEC 61000-4-
2 ESD Contact Discharge test.
Machine Model
The machine model for ESD tests all pins using a 200pF
storage capacitor and zero discharge resistance.
The objective is to emulate the stress caused when I/O
pins are contacted by handling equipment during test
and assembly.
The Air-Gap Discharge Method involves approaching the
device with a charged probe. The Contact Discharge
Method connects the probe to the device before the
probe is energized.
Applications Information
Typical Operating Circuit
The Typical Operating Circuit shows the MAX4927 in a
1000 Base-T docking station application.
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum ratings.
Stresses beyond the listed ratings may cause perma-
nent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply VDD before applying
analog signals, especially if the analog signal is not
current limited.
Power-Supply Bypassing
Bypass at least one VDD input to ground with a 0.1F or
larger ceramic capacitor as close to the device as pos-
sible. Use the smallest physical size possible for optimal
performance (0603 body size is recommended).
It is also recommended to bypass more than one VDD
input. A good strategy is to bypass one VDD input with
a 0.1F capacitor, and at least a second VDD input with
a 10nF capacitor (use 0603 or smaller physical size
ceramic capacitor).
Layout
High-speed switches require proper layout and design
procedures for optimum performance. Keep design-con-
trolled-impedance PCB traces as short as possible.
Ensure that bypass capacitors are as close as possible
to the device. Use large ground planes where possible.
Chip Information
PROCESS: BiCMOS
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