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| 型号： | MAX4929EETP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/13页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HDMI 2:1 20-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 开关，DVI/HDMI |
| 电路： | 1 x 2:1 |
| 导通状态电阻： | 25 欧姆 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
MAX4929E
HDMI 2:1 Low-Frequency Translating Switch
8
_______________________________________________________________________________________
Logic Outputs
The HPDO_ signals are 5V TTL-compatible, per HDMI/
DVI specifications. HPIRO is VL compatible.
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly.
Additionally, the MAX4929E is protected to ±6kV (HBM)
on SCL1, SCL2, SDA1, SDA2, HPDO1, HPDO2, HPIR1,
and HPIR2 by the HBM.
Human Body Model
Several ESD testing standards exist for measuring the
robustness against ESD events. The ESD protection of
the MAX4929E is characterized with the HBM method.
Figure 4 shows the model used to simulate an ESD event
resulting from contact with the human body. The model
consists of a 100pF storage capacitor that is charged to a
high voltage, then discharged through a 1.5kΩ resistor.
Figure 5 shows the current waveform when the storage
capacitor is discharged into a lower impedance.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report documenting test
setup, methodology, and results.
Figure 4. Human Body ESD Test Model
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
Ω
RD
1500
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
INPUTS
SEL
HIZ1
HIZ2
SWITCH CONNECTIONS
0
1
SDAO to SDA1, SCLO to SCL1
0
1
0
SDAO to SDA1, SCLO to SCL1
1
0
1
SDAO to SDA2, SCLO to SCL2
1
0
SDAO to SDA2, SCLO to SCL2
X
0
High Impedance
X
1
High Impedance
Table 1. Inputs Selection for 2:1 Mux
Truth Table
INPUTS
OUTPUTS
SEL
HPD
HIZ1
HIZ2
HPDO1
HPDO2
X0
0
1
0
00
01
0
1
0
10
11
0
1
0
01
XX
1
High
Impedance
High
Impedance
XX
0
High
Impedance
High
Impedance
Table 2. HPD Output Channel Selection
INPUTS
OUTPUT
SEL
HPIR1
HPIR2
HIZ1
HIZ2
HPIRO
X0
0
1
0
X1
1
0
1
0
1
00
X
0
1
0
01
X
0
1
0
1
1X
0
1
0
1X
1
0
1
0
1
XXX
0
High
Impedance
XXX
1
High
Impedance
Table 3. HPIRO Output Channel Selection
INPUTS
OUTPUTS
HIZ1
HIZ2
MODE OF OPERATION
00
High Impedance: SDAO, SDA1, SDA2,
SCLO, SCL1, SCL2, HPDO1, HPDO2, HPIRO
0
1
Normal Operation
1
0
Normal Operation
11
High Impedance: SDAO, SDA1, SDA2,
SCLO, SCL1, SCL2, HPDO1, HPDO2, HPIRO
Table 4. Mode of Operation
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