参数资料
型号: MAX4936CTN+
厂商: Maxim Integrated Products
文件页数: 15/19页
文件大小: 0K
描述: IC TRANSMIT/RCVR SWITCH 56-TQFN
应用说明: Ultrasound Imaging Systems Application Note
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 27
功能: 开关
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 1.62 V ~ 5.5 V,±1.35 V ~ 2.75 V
电流 - 电源: 1.5mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(5x11)
包装: 管件
_______________________________________________________________________________________ 5
MAX4936–MAX4939
Octal High-Voltage Transmit/Receive Switches
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.62V to +5.5V, VCC = +2.7V to +5.5V, VEE = -2.7V to -5.5V, VCLR = 0V, LVCC_ = VCC, LVEE_ = VEE, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
Note 2: All specifications are 100% production tested at TA = +70NC, unless otherwise noted. Specifications at 0NC are guaran-
teed by design.
Note 3: See the Ultrasound-Specific IMD3 Specification section.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Logic Supply Current
IDD
CLR, DIN, CLK, LE = GND or VDD
+1
F
A
Positive Analog Supply Current
ICC
Per channel, switch is on, VCC = +5V,
VEE = -5V, ICH = 1.5mA
+1.15
+1.5
+2
mA
Positive Analog Shutdown
Supply Current
ICC_SHDN
CLR = high
+1
F
A
Negative Analog Supply
Current
IEE
Per channel, switch is on, VCC = +5V,
VEE = -5V, ICH = 1.5mA
-2
-1.5
-1.15
mA
Negative Analog Shutdown
Supply Current
IEE_SHDN
CLR = high
-1
F
A
On Power-Supply Rejection
Ratio
PSRRON
VCC to NO_ or VEE to NO_, switch is on,
VCC = +5V, VEE = -5V, RL = 200I,
CL = 30pF, ICH = 1.5mA, f = 1MHz
-77
dB
Off Power-Supply Rejection
Ratio
PSRROFF
VCC to NO_ or VEE to NO_, switch is off,
VCC = +5V, VEE = -5V, RL = 200I,
CL = 30pF, f = 1MHz
-80
dB
LOGIC TIMING (CLR, DIN, DOUT, CLK, LE) (Figure 1)
CLK Period
tCP
VDD = 3V Q10%
50
ns
VDD = 1.8V Q10%
100
CLK High Time
tCH
VDD = 3V Q10%
20
ns
VDD = 1.8V Q10%
45
CLK Low Time
tCL
VDD = 3V Q10%
20
ns
VDD = 1.8V Q10%
45
CLK to DOUT Delay
tDO
VDD = 3V Q10%, CL P 20pF
3
30
ns
VDD = 1.8V Q10%, CL P 20pF
7
70
DIN to CLK Setup Time
tDS
VDD = 3V Q10%
10
ns
VDD = 1.8V Q10%
16
DIN to CLK Hold Time
tDH
VDD = 3V Q10%
4
ns
VDD = 1.8V Q10%
4
CLK to LE Setup Time
tCS
VDD = 3V Q10%
36
ns
VDD = 1.8V Q10%
65
LE Low Pulse Width
tWL
VDD = 3V Q10%
14
ns
VDD = 1.8V Q10%
22
CLR High Pulse Width
tWC
VDD = 3V Q10%
20
ns
VDD = 1.8V Q10%
40
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