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参数资料
| 型号： | MAX5019ESA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO PWM 8SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 302kHz |
| 占空比： | 85% |
| 电源电压： | 13 V ~ 110 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
Current-Mode PWM Controllers with Integrated
Startup Circuit
V DSMAX ≥ 7 2 V × ? 1 +
? = 144 V
?
?
14 ?
14 ?
7) Choose the inductor value so that the peak ripple
current (LIR) in the inductor is between 10% and
20% of the maximum output current.
Choose MOSFETs with appropriate avalanche
power ratings.
L ≥
( V OUT + V D ) × ( 1 - D MIN )
2 × LIR × 275 kHz × I OUTMAX
× N P ≤ N T ≤
V DDMAX + 0 . 7
( 5 . 5 ) × ( 1 - 0 . 198 )
0 . 4 × 275 kHz × 10 A
5) Choose the tertiary winding turns ratio (N T /N P ) so
that the minimum input voltage provides the mini-
mum operating voltage at V DD (13V). Use the follow-
ing equation to calculate the tertiary winding turns
ratio:
V DDMIN + 0 . 7
V IN_MIN
× N P
V IN_MAX
where:
V DDMIN is the minimum V DD supply voltage (13V).
V DDMAX is the maximum V DD supply voltage (36V).
V IN_MIN is the minimum input supply voltage (36V).
V IN_MAX is the maximum input supply voltage (72V
in this design example).
N P is the number of turns of the primary winding.
N T is the number of turns of the tertiary winding.
where V D is the output Schottky diode forward volt-
age drop (0.5V).
L ≥ = 4 . 01 μ H
8) The size and ESR of the output filter capacitor deter-
mine the output ripple. Choose a capacitor with a
low ESR to yield the required ripple voltage.
Use the following equations to calculate the peak-to-
peak output ripple:
2 2
V RIPPLE = V RIPPLE , ESR + V RIPPLE , C
where:
V RIPPLE is the combined RMS output ripple due to
V RIPPLE,ESR , the ESR ripple, and V RIPPLE,C , the
capacitive ripple. Calculate the ESR ripple and
capacitive ripple as follows:
V RIPPLE,ESR = I RIPPLE x ESR
× 1 4 ≤ N T ≤ × 14
13 . 7
36
36 . 7
72
V RIPPLE,C = I RIPPLE /(2 x π x 275kHz x C OUT )
5 . 33 ≤ N T ≤ 7 . 14
Choose N T = 6.
6) Choose R SENSE according to the following equation:
Layout Recommendations
All connections carrying pulsed currents must be very
short, be as wide as possible, and have a ground plane
as a return path. The inductance of these connections
R SENSE ≤
N S
N P
V ILIM
× 1 . 2 × I OUTMAX
must be kept to a minimum due to the high di/dt of the
currents in high-frequency switching power converters.
Current loops must be analyzed in any layout pro-
posed, and the internal area kept to a minimum to
where:
V ILim is the current-sense comparator trip threshold
voltage (0.465V).
N S /N P is the secondary side turns ratio (5/14 in this
example).
I OUTMAX is the maximum DC output current (10A in
this example).
reduce radiated EMI. Ground planes must be kept as
intact as possible.
Chip Information
TRANSISTOR COUNT: 589
PROCESS: BiCMOS
× 1 . 2 × 10
R SENSE ≤
0 . 465 V
5
14
= 109 m ?
12
______________________________________________________________________________________
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