参数资料
型号: MAX5035EVKIT
厂商: Maxim Integrated Products
文件页数: 12/17页
文件大小: 0K
描述: EVAL KIT FOR MAX5035
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 5V
电流 - 输出: 1A
输入电压: 8 ~ 76V
稳压器拓扑结构: 降压
频率 - 开关: 125kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: MAX5035
MAX5035
1A, 76V, High-Efficiency MAXPower
Step-Down DC-DC Converter
Ensure that the ripple specification of the input capaci-
tor exceeds the worst-case capacitor RMS ripple cur-
capacitance and the ESR required for a specified rip-
ple using the following equations:
rent. Use the following equations to calculate the input
capacitor RMS current:
I CRMS = I PRMS 2 ? I AVGIN 2
ESR OUT =
? V OESR
? I L
( I PK DC ( PK DC ) ) × D
? I L
2 . 2 × ? V OQ × f SW
where :
I PRMS =
I AVGIN =
2 + I 2 + I × I
V O UT × I OUT
V IN × η
C OUT ≈
The MAX5035 has an internal soft-start time (t SS ) of
400μs. It is important to keep the output rise time at
startup below t SS to avoid output overshoot. The output
? I L ? I L
I PK = I OUT + , I DC = I OUT ?
and D =
? V OESR
C OUT = STEP RESPONSE
2 2
V OUT
V IN
I PRMS is the input switch RMS current, I AVGIN is the
input average current, and η is the converter efficiency.
The ESR of aluminum electrolytic capacitors increases
significantly at cold temperatures. Use a 1μF or greater
value ceramic capacitor in parallel with the aluminum
electrolytic input capacitor, especially for input voltages
below 8V.
Output Filter Capacitor
The worst-case peak-to-peak and RMS capacitor ripple
current, allowable peak-to-peak output ripple voltage,
and the maximum deviation of the output voltage dur-
ing load steps determine the capacitance and the ESR
requirements for the output capacitors.
The output capacitance and its ESR form a zero, which
improves the closed-loop stability of the buck regulator.
Choose the output capacitor so the ESR zero frequency
(f Z ) occurs between 20kHz to 40kHz. Use the following
equation to verify the value of f Z . Capacitors with 100m ?
to 250m ? ESR are recommended to ensure the closed-
loop stability, while keeping the output ripple low.
rise time is directly proportional to the output capacitor.
Use 68μF or lower capacitance at the output to control
the overshoot below 5%.
In a dynamic load application, the allowable deviation
of the output voltage during the fast-transient load dic-
tates the output capacitance value and the ESR. The
output capacitors supply the step load current until the
controller responds with a greater duty cycle. The
response time (t RESPONSE ) depends on the closed-
loop bandwidth of the converter. The resistive drop
across the capacitor ESR and capacitor discharge
cause a voltage droop during a step load. Use a com-
bination of low-ESR tantalum and ceramic capacitors
for better transient load and ripple/noise performance.
Keep the maximum output-voltage deviation above the
tolerable limits of the electronics being powered.
Assuming a 50% contribution each from the output
capacitance discharge and the ESR drop, use the fol-
lowing equations to calculate the required ESR and
capacitance value:
ESR OUT =
I STEP
I × t
? V OQ
f Z =
1
2 × π × C OUT × ESR OUT
where I STEP is the load step and t RESPONSE is the
response time of the controller. Controller response
The output ripple is comprised of ? V OQ (caused by the
capacitor discharge) and ? V OESR (caused by the ESR
of the capacitor). Use low-ESR tantalum or aluminum
electrolytic capacitors at the output. Assuming that the
contributions from the ESR and capacitor discharge
equal 80% and 20% respectively, calculate the output
12
time is approximately one-third of the reciprocal of the
closed-loop unity-gain bandwidth, 20kHz typically.
PCB Layout Considerations
Proper PCB layout is essential. Minimize ground noise
by connecting the anode of the Schottky rectifier, the
input bypass capacitor ground lead, and the output fil-
ter capacitor ground lead to a single point ( “star ”
Maxim Integrated
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