参数资料
型号: MAX5038EAI33+
厂商: Maxim Integrated Products
文件页数: 9/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 46
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
Dual-Phase, Parallelable, Average Current-Mode
Controllers
Pin Description
PIN
1, 13
2, 14
3
4
5, 7
6
8
9
10
11
12
15
16, 26
17, 25
18, 24
19, 23
20
21
22
27
28
NAME
CSP2,
CSP1
CSN2,
CSN1
PHASE
PLLCMP
CLP2,
CLP1
SGND
SENSE+
SENSE-
DIFF
EAN
EAOUT
EN
BST1,
BST2
DH1,
DH2
LX1, LX2
DL1, DL2
V CC
IN
PGND
CLKOUT
CLKIN
FUNCTION
Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
Current-Sense Differential Amplifier Negative Input. Senses the inductor current.
Phase-Shift Setting Input. Connect PHASE to V CC for 120 ° , leave PHASE unconnected for 90 ° , or connect
PHASE to SGND for 60 ° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
External Loop-Compensation Input. Connect compensation network for the phase lock loop (see Phase-
Locked Loop section).
Current-Error Amplifier Output. Compensate the current loop by connecting an RC network to ground.
Signal Ground. Ground connection for the internal control circuitry.
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
V OUT+ at the load. The MAX5038 regulates the difference between SENSE+ and SENSE- according to the
factory preset output voltage. The MAX5041 regulates the SENSE+ to SENSE- difference to +1.0V.
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
V OUT- or PGND at the load.
Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.
Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.
Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error
amplifier gain-setting resistors determine the amount of adaptive voltage positioning
Output Enable. A logic low shuts down the power drivers. EN has an internal 5μA pullup current.
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply.
Connect 0.47μF ceramic capacitors between BST_ and LX_.
High-Side Gate Driver Output. Drives the gate of the high-side MOSFET.
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for
the high-side driver.
Low-Side Gate Driver Output. Synchronous MOSFET gate drivers for the two phases.
Internal +5V Regulator Output. V CC is derived internally from the IN voltage. Bypass to SGND with 4.7μF
and 0.1μF ceramic capacitors.
Supply Voltage Connection. Connect IN to V CC for a +5V system. Connect the VRM input to IN through an
RC lowpass filter, a 2.2 ? resistor and a 0.1μF ceramic capacitor.
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and V CC bypass capacitor
returns together.
Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount specified by PHASE. Use CLKOUT
to parallel additional MAX5038/MAX5041s.
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz.
The PWM frequency defaults to the internal oscillator if CLKIN is connected to V CC or SGND. Connect
CLKIN to SGND to set the internal oscillator to 250kHz or connect to V CC to set the internal oscillator to
500kHz. CLKIN has an internal 5μA pulldown current.
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