参数资料
型号: MAX5065EAI+T
厂商: Maxim Integrated Products
文件页数: 7/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 带卷 (TR)
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T A = +25 ° C, unless otherwise noted.)
DRIVER RISE TIME
DRIVER FALL TIME
HIGH-SIDE DRIVER (DH_)
120
vs. DRIVER LOAD CAPACITANCE
120
vs. DRIVER LOAD CAPACITANCE
SINK AND SOURCE CURRENT
MAX5065/67 toc21
110
100
90
80
110
100
90
80
70
60
50
DL_
DH_
70
60
50
DL_
DH_
DH_
1.6A/div
40
30
40
30
20
10
0
1
6
11
16
21
V IN = +12V
f SW = 250kHz
26 31
36
20
10
0
1
6
11
16
21
V IN = +12V
f SW = 250kHz
26 31
36
V IN = +12V
C DH_ = 22nF
100ns/div
C DRIVER (nF)
C DRIVER (nF)
PLL LOCKING TIME
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
MAX5065/67 toc22
CLKOUT
5V/div
250kHz TO 350kHz AND
350kHz TO 250kHz MAX5065/67 toc23
350kHz
V IN = +12V
C DL_ = 22nF
100ns/div
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHz MAX5065/67 toc24
DL_
1.6A/div
PLLCMP
200mV/div
0
250kHz
V IN = +12V
NO LOAD
100 μ s/div
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz MAX5065/67 toc25
CLKOUT
5V/div
CLKOUT
5V/div
250kHz
PLLCMP
500kHz
200mV/div
PLLCMP
200mV/div
0
250kHz
100 μ s/div
V IN = +12V
NO LOAD
0
V IN = +12V
NO LOAD
150kHz
100 μ s/div
_______________________________________________________________________________________
7
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