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参数资料
| 型号： | MAX5072ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/27页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BST ADJ 1A/2A 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 28 V |
| 输入电压： | 4.5 V ~ 23 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 1A，2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
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2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
Input Voltage (V+)/Internal Linear
Regulator (VL)
All internal control circuitry operates from an internally
regulated nominal voltage of 5.2V (VL). At higher input
voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V. At
5.5V or below, the internal linear regulator operates in
dropout mode, where VL follows V+. Depending on the
load on VL, the dropout voltage can be high enough to
reduce VL below the undervoltage lockout (UVLO)
threshold.
For input voltages of less than 5.5V, connect V+ and VL
together. The load on VL is proportional to the switch-
ing frequency of converter 1 and converter 2. See the
VL Dropout Voltage vs. Each Converter Switching
Frequency graph in the Typical Operating
Characteristics . For input voltage ranges higher than
5.5V, use the internal regulator.
Bypass V+ to SGND with a low-ESR, 0.1μF or greater
ceramic capacitor placed close to the MAX5072. Current
spikes from VL may disturb internal circuitry powered by
VL. Bypass VL with a low-ESR, ceramic 0.1μF capacitor
to PGND and a 4.7μF capacitor to SGND.
Undervoltage Lockout/Soft-Start
The MAX5072 includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for smooth con-
verter turn-on and monotonic rise of the output voltage.
The rising UVLO threshold is internally set to 4.3V with
a 175mV hysteresis. Hysteresis at UVLO eliminates
“chattering ” during startup. When VL drops below
UVLO, the internal switches are turned off and RST is
forced low.
Digital soft-start/soft-stop is provided internally to
reduce input surge currents and glitches at the input
during turn-on/turn-off. When UVLO is cleared and EN_
is high, digital soft-start slowly ramps up the internal
reference voltage in 64 steps. The total soft-start period
is 2048 switching cycles of the internal oscillator.
To calculate the soft-start period, use the following
equation:
Enable
The MAX5072 dual converter provides separate enable
inputs EN1 and EN2 to individually control or sequence
the output voltages. These active-high enable inputs are
TTL compatible. Pulling EN_ high ramps up the reference
slowly, which provides soft-start at the outputs. Forcing
the EN_ low externally disables the individual output and
generates a RST signal. Use EN1, EN2, and PGOOD1 for
sequencing (see Figure 4). Connect PGOOD1 to EN2 to
make sure converter 1’s output is within regulation before
converter 2 starts. Add an RC network from VL to EN1
and EN2 to delay the individual converter. A larger RC
time constant means a more delayed output. Sequencing
reduces input inrush current and possible chattering.
Connect the EN_ to VL for always-on operation.
MR
Microprocessor-based products require manual reset
capability, allowing the operator or external logic circuitry
to initiate a reset. A logic low on MR asserts reset. Reset
remains asserted while MR is low, and for the Reset
Active Timeout Period (t RP ) after MR returns high. MR
has an internal 44k ? pullup resistor to VL, so it can be
left unconnected if not used. MR can be driven to TTL
logic levels.
Connect a normally open momentary switch from MR to
SGND to create a manual reset function. Note that
external debounce circuitry is not required. If MR is dri-
ven from long cables or if the device is used in a noisy
environment, connect a 0.1μF capacitor from MR to
SGND to provide additional noise immunity.
RST Output
RST is an open-drain output. RST pulls low when either
output falls below 92.5% of its nominal regulation volt-
age. Once both outputs exceed 92.5% of their nominal
regulated voltages and both soft-start cycles are com-
pleted, RST enters a high-impedance state after the
180ms active timeout period. To obtain a logic-voltage
output, connect a pullup resistor from RST to a logic
supply voltage. The internal open-drain MOSFET can
sink 3mA while providing a TTL logic-low signal. If
t SS =
2048
f OSC
unused, ground RST or leave it unconnected.
PGOOD1
In addition to RST , converter 1 also includes a power-
where f OSC is the internal oscillator frequency in hertz,
which is twice the switching frequency of each converter.
good flag. Pull PGOOD1 to a logic voltage to provide
logic-level output. PGOOD1 is an open-drain output and
can sink 3mA while providing the TTL logic-low
signal. PGOOD1 goes low when converter 1’s output
drops to 92.5% of its nominal regulated voltage. Connect
PGOOD1 to SGND or leave unconnected, if not used.
______________________________________________________________________________________
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相关代理商/技术参数 |
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| MAX5072EVKIT | 功能描述:电源管理IC开发工具 2.2MHz Buck or Boost Converter RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| MAX5073 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:2.2MHz, Dual-Output Buck or Boost Converter with Internal Power MOSFETs |
| MAX5073ATI | 功能描述:直流/直流开关转换器 RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| MAX5073ATI+ | 功能描述:直流/直流开关转换器 2.2MHz Buck or Boost Converter RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| MAX5073ATI+T | 功能描述:直流/直流开关转换器 2.2MHz Buck or Boost Converter RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
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