参数资料
型号: MAX5077AUD
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: MOSFETs
英文描述: Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output
中文描述: 5 A PUSH-PULL BASED MOSFET DRIVER, PDSO14
封装: 4.4 MM, MO-153ABT-1, TSSOP-14
文件页数: 5/9页
文件大小: 235K
代理商: MAX5077AUD
M
Push-Pull FET Driver with Integrated Oscillator
and Programmable Clock Output
_______________________________________________________________________________________
5
Pin Description
PIN
1, 8
2
NAME
N.C.
SEL1
FUNCTION
No Connection. Must be left unconnected.
CLK Frequency Ratio Select Input. Use SEL1 and SEL2 to set f
CLK
to f
NDRV_
frequency ratio (see Table 1).
3
CLK
Synchronizing Clock Output. Clock output with a ±10mA peak current drive that can be used to synchronize
an external PWM regulator. CLK/NDRV_ frequency has a 1x, 2x, or 4x ratio (see the
Synchronizing Clock
Output
section).
4, 14
I.C.
Connect to ground. Internal function.
5
RT
Oscillator Timing Resistor Connection. Bypass RT with a 1nF capacitor to AGND. Connect a resistor from
RT to AGND to set the internal oscillator frequency.
6
7
9
10
11
12
13
EP
AGND
DGND
PGND
NDRV1
NDRV2
V
CC
SEL2
EP
Analog Ground. Connect AGND to ground plane.
Digital Ground. Connect DGND to ground plane.
Power Ground. Connect to ground plane.
Gate Driver 1. Connect NDRV1 to the gate of an external n-channel FET.
Gate Driver 2. Connect NDRV2 to the gate of an external n-channel FET.
Power-Supply Input. Bypass V
CC
to PGND with 0.1μF||1μF ceramic capacitors.
CLK Frequency Divisor Input. Use SEL1 and SEL2 to set f
CLK
to f
NDRV_
frequency ratio (see Table 1).
Exposed Pad. Internally connected to DGND. Connect exposed pad to ground plane.
MAX5077
T-FF
Q
Q
UVLO 3.5V
V
CC
NDRV2
NDRV1
PGND
I.C.
I.C.
Q
V
CC
SEL1
SEL2
DGND
RT
AGND
Q
Q
OSC
5V
LDO
Q
CLK
INTERNAL
FUNCTION
N.C.
Figure 1. MAX5077 Functional Diagram
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