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参数资料
| 型号： | MAX5083ATE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 16TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.23 V ~ 32 V |
| 输入电压： | 7.5 V ~ 40 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 250kHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TQFN-EP（5x5） |
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
IN
LDO
ON/OFF
>1.23V ON
DVREG
C-
C+
DVREG
REG
EN
1.23V
1.23V
<1.11V OFF
PCLK
LEVEL
SHIFT
SGND
MAX5082
I SS
REF
V REF
THERMAL
SHDN
EN
OVERL
OVERLOAD
MANAGEMENT
ILIM
CLK
REGOK
SS
1.23V
E/A
SSA
ILIM
REF_ILIM
IN
FB
COMP
V REF
PFM
REF_PFM
HIGH-SIDE
CURRENT
SENSE
BST
IN
CPWM
LOGIC
LX
SYNC
EN
OSC
RAMP
DVREG
0.3V
CLK
CHARGE-PUMP
MANAGEMENT
PCLK
SCLK
PGND
Figure 1. MAX5082 Simplified Block Diagram
Internal Linear Regulator (REG)
REG is the output terminal of a 5V (MAX5082), or 8V
(MAX5083) LDO which is powered from IN and pro-
vides power to the IC. Connect REG externally to
DVREG to provide power for the high-side MOSFET
gate driver. Bypass REG to SGND with a ceramic
capacitor of at least 1μF. Place the capacitor physically
close to the MAX5082/MAX5083 to provide good
bypassing. During normal operation, REG is intended
for powering up only the internal circuitry and should
not be used to supply power to external loads.
Internal UVLO/External UVLO
The MAX5082/MAX5083 provides two undervoltage
lockouts (UVLOs). An internal UVLO looks at the input
voltage (V IN ) and is fixed at 4.1V (MAX5082) or 7.1V
(MAX5083). An external UVLO is sensed and pro-
grammed at the ON/ OFF pin. The external UVLO over-
rides the internal UVLO when the external UVLO is
higher than the internal UVLO. During startup, before
any operation begins, the input voltage and the voltage
at ON/ OFF must exceed their respective UVLOs. The
external UVLO has a rising threshold of 1.23V with
0.12V of hysteresis. Program the external UVLO by
connecting a resistive divider from IN to ON/ OFF to
SGND. Connect ON/ OFF to IN directly to disable the
external UVLO.
Driving ON/ OFF to ground places the MAX5082/
MAX5083 in shutdown. When in shutdown, the internal
power MOSFET turns off, all internal circuitry shuts
down and the quiescent supply current reduces to
200μA. Connect an RC network from ON/ OFF to SGND
to set a turn-on delay that can be used to sequence the
output voltages of multiple devices.
8
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