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参数资料
| 型号： | MAX5089ATE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2A 16TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 20 V |
| 输入电压： | 4.5 V ~ 23 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 312kHz ~ 2.1MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-TQFN-EP（5x5） |
2.2MHz, 2A Buck Converters with an
Integrated High-Side Switch
Calculate the modulator gain (G M ) at the crossover fre-
First, select the crossover frequency so that:
f C ≤ SW
quency.
G M =
VIN
VOSC
×
ESR
ESR + ( 2 π × fc × L)
×
VFB
VOUT
f
20
Calculate the LC double-pole frequency, f LC :
where V OSC is the 1V P-P ramp amplitude and V FB = 0.6V.
The transconductance error amplifier gain at f C is:
f LC =
1
2 π × L × C OUT
G E/A = g m x R F
The total loop gain at f C should be equal to 1:
G M = G E/A = 1
Place a zero f Z =
1
2 π × R F × C F
at 0.75 × f LC
or
R F =
V OSC (ESR + 2 π × f C × L)V OUT
V FB × V IN × g m × ESR
where:
C F =
with R F ≥ 10k ? .
1
2 π × 0.75 × f LC × R F
Place a zero at or below the LC double pole:
Calculate C A for a target unity crossover frequency, f C :
C F =
1
2 π × R F × f LC
C A =
2 π × f C × L × C OUT × V OSC
V IN × R F
Place a high-frequency pole at f P = 0.5 x f SW . Therefore
C CF is:
Place a pole ( f P 1 =
1
2 π × R A × C A
) at f ZESR .
C CF =
1
π × R F × f SW
R A =
1
2 π × f ZESR × C A
Procedure 2 (see Figure 4)
When using a low-ESR ceramic-type capacitor as the
Place a second zero, f Z2 , at 0.2 x f C or at f LC , whichev-
er is lower.
output capacitor, the ESR frequency is much higher
than the targeted unity-gain crossover frequency (f C ).
In this case, Type III compensation is recommended.
R 1 =
1
2 π × f Z2 × C A
? R A
= = 5
Place a second pole (f P2 =
2 π × R F CF
× C
C CF =
Type III compensation provides a low-frequency pole
( ≈ DC) and two pole-zero pairs. The locations of the
zero and poles should be such that the phase margin
peaks at f C .
f C f P
The f Z f C is a good number to get approximate-
ly 60° of phase margin at f C . However, it is important to
place the two zeros at or below the double pole to
avoid conditional stability.
1
)
at 1/2 the switching frequency.
C F
(2 π × 0.5 × f SW × R F × C F ) -1
______________________________________________________________________________________
17
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