参数资料
型号: MAX5121BEEE
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: DAC
英文描述: +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference
中文描述: SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO16
封装: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件页数: 8/20页
文件大小: 288K
代理商: MAX5121BEEE
M
+3V /+5V, 12-Bit, S erial Voltage-Output DACs
with Internal Referenc e
8
_______________________________________________________________________________________
Typic al Operating Charac teristic s (c ontinued)
(V
DD
= +5V (MAX5120), V
DD
= +3V (MAX5121), R
L
= 5k
, C
L
= 100pF, OS = AGND, T
A
= +25°C, unless otherwise noted.)
CS
2V/div
OUT
500mV/div
2
μ
s/div
MAX5121
DYNAMIC RESPONSE FALL TIME
MAX5120/21-22
SCLK
2V/div
OUT
500
μ
V/div
AC COUPLED
2
μ
s/div
MAX5121
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5120/21-23
CS
2V/div
OUT
100mV/div
AC COUPLED
5
μ
s/div
MAX5121
MAJOR CARRY TRANSITION
MAX5120/21-24
Pin Desc ription
PIN
Offset Adjust (Analog Input)
Analog Output Voltage. High impedance if part is in shutdown.
OS
OUT
1
2
FUNCTION
NAME
Power-Down Lockout (Digital Input)
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).
PDL
4
Reset Value Input (Digital Input)
1: Tie to V
DD
to select midscale as the output reset value.
0: Tie to DGND to select 0V as the output reset value.
RSTVAL
3
Active-Low Chip-Select Input (Digital Input)
Serial Data Input. Data is clocked in on the rising edge of SCLK.
CS
DIN
6
7
Serial Clock Input
Digital Ground
SCLK
DGND
8
9
Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.
CLR
5
Serial Data Output
User-Programmable Output (Digital Output)
DOUT
UPO
10
11
Power-Down Input (Digital Input). Pulling PD high when
PDL
= V
DD
places the IC into shutdown with a
maximum shutdown current of 20μA.
PD
12
Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5120) or +1.25V (MAX5121) nominal output, externally adjustable at REFADJ . In external reference
mode, disable the internal reference by pulling REFADJ to V
DD
and applying the external reference to REF.
REF
14
Positive Power Supply. Bypass with a 0.1μF capacitor in parallel with a 4.7μF capacitor to AGND.
V
DD
16
Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to V
DD
when using an
external reference.
REFADJ
15
Analog Ground
AGND
13
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