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参数资料
| 型号： | MAX5155BEEE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT DUAL LP SER 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 设置时间： | 15µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 667mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极；2 电压，双极 |
| 采样率（每秒）： | * |
MAX5154/MAX5155
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Serial Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—MAX5154 (continued)
(VDD = +5V ±10%, VREFA = VREFB = 2.048V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA= +25°C (OS_ tied to AGND for a gain of +2V/V).)
Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end
points.
Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.
Note 4: SCLK minimum clock period includes the rise and fall times.
CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p
ISOURCE = 2mA
(Note 4)
(Note 3)
ns
Rail-to-rail (Note 2)
To 1/2LSB of full-scale, VSTEP = 4V
40
ISINK = 2mA
tCL
SCLK Pulse Width Low
CONDITIONS
ns
40
tCH
SCLK Pulse Width High
nV-s
5
Digital Crosstalk
nV-s
5
Digital Feedthrough
s
25
Time Required to Exit Shutdown
k
24
34
ROS_
OSA or OSB Input Resistance
ns
100
tCP
SCLK Clock Period
A
0
±1
Reference Current in Shutdown
A
2
10
IDD(SHDN)
Power-Supply Current
in Shutdown
mA
0.5
0.65
IDD
Power-Supply Current
V
4.5
5.5
VDD
Positive Supply Voltage
ns
40
tDS
SDI Setup Time
ns
V
VDD - 0.5
VOH
Output High Voltage
0
tCSH
SCLK Rise to CS Rise
Hold Time
ns
40
tCSS
CS Fall to SCLK Rise
Setup Time
CLOAD = 200pF
V
0 to VDD
Output Voltage Swing
s
15
Output Settling Time
CLOAD = 200pF
ns
80
V
0.13
0.40
VOL
Output Low Voltage
V/s
0.75
SR
Voltage Output Slew Rate
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
tDO2
SCLK Fall to DOUT
Valid Propagation Delay
ns
80
tDO1
SCLK Rise to DOUT
Valid Propagation Delay
ns
0
tDH
SDI Hold Time
ns
100
tCSW
CS Pulse Width High
ns
40
tCS1
CS Rise to SCLK Rise Hold
ns
10
tCS0
SCLK Rise to CS Fall Delay
DIGITAL OUTPUTS (DOUT, UPO)
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
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